Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 355
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 25-4: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM
FIGURE 25-5: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM
SELSRCA<3:0>
SELSRCB<3:0>
SELSRCC<3:0>
AND
CMxMSKCON
MUX A
MAI
MBI
MCI
Comparator Output
To Digital
Signals
Filter
OR
Blanking
Blanking
Blanking
Signals
Signals
ANDI
MASK
“AND-OR” Function
HLMS
MUX BMUX C
Blanking
Logic
(CMxMSKCON<15)
(CMxMSKSRC<11:8)
(CMxMSKSRC<7:4)
(CMxMSKSRC<3:0>)
MBI
MCI
MAI
MBI
MCI
MAI
CXOUT
CFLTREN
Digital Filter
TxCLK
(1,2)
SYNCO1
(3)
FP
(4)
FOSC
(4)
CFSEL<2:0>
 CFDIV
Note 1: See the Type C Timer Block Diagram (Figure 13-2).
2: See the Type B Timer Block Diagram (Figure 13-1).
3: See the High-Speed PWMx Module Register Interconnection Diagram (Figure 16-2).
4: See the Oscillator System Diagram (Figure 9-1).
From Blanking Logic
1xx
010
000
001
1
0
(CM
xFLTR<6:4>)
(CM xFLTR<3>)