Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 347
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 24-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —PTGQPTR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Unimplemented: Read as ‘0’
bit 4-0 PTGQPTR<4:0>: PTG Step Queue Pointer Register bits
This register points to the currently active Step command in the Step queue.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 24-13: PTGQUEx: PTG STEP QUEUE REGISTER x (x = 0-7)
(1,3)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STEP(2x + 1)<7:0>
(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STEP(2x)<7:0>
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 STEP(2x + 1)<7:0>: PTG Step Queue Pointer Register bits
(2)
A queue location for storage of the STEP(2x + 1) command byte.
bit 7-0 STEP(2x)<7:0>: PTG Step Queue Pointer Register bits
(2)
A queue location for storage of the STEP(2x) command byte.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: Refer to Table 24-1 for the Step command encoding.
3: The Step registers maintain their values on any type of Reset.