Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 329
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 23-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NB<1:0> CH123SB
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NA<1:0> CH123SA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXB bits
In 12-bit mode (AD21B =
1), CH123NB is Unimplemented and is Read as ‘0’:
bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample MUXB bit
In 12-bit mode (AD21B = 1), CH123SB is Unimplemented and is Read as ‘0’:
bit 7-3 Unimplemented: Read as ‘0’
bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXA bits
In 12-bit mode (AD21B =
1), CH123NA is Unimplemented and is Read as ‘0’:
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
Value
ADC Channel
CH1 CH2 CH3
11 AN9 AN10 AN11
10
(1,2)
OA3/AN6 AN7 AN8
0x V
REFL VREFL VREFL
Value
ADC Channel
CH1 CH2 CH3
1
(2)
OA1/AN3 OA2/AN0 OA3/AN6
0
(1,2)
OA2/AN0 AN1 AN2
Value
ADC Channel
CH1 CH2 CH3
11 AN9 AN10 AN11
10
(1,2)
OA3/AN6 AN7 AN8
0x V
REFL VREFL VREFL