Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 251
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 6-4 INTDIV<2:0>: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter),
velocity counter and index counter internal clock divider select)
(3)
111 = 1:128 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
bit 3 CNTPOL: Position and Index Counter/Timer Direction Select bit
1 = Counter direction is negative unless modified by external up/down signal
0 = Counter direction is positive unless modified by external up/down signal
bit 2 GATEN: External Count Gate Enable bit
1 = External gate signal controls position counter operation
0 = External gate signal does not affect position counter/timer operation
bit 1-0 CCM<1:0>: Counter Control Mode Selection bits
11 = Internal Timer mode with optional external count is selected
10 = External clock count with optional external count is selected
01 = External clock count with external up/down direction is selected
00 = Quadrature Encoder Interface (x4 mode) Count mode is selected
REGISTER 17-1: QEI1CON: QEI CONTROL REGISTER (CONTINUED)
Note 1: When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
2: When CCM<1:0> = 00 and QEA and QEB values match Index Match Value (IMV), the POSCNTH and
POSCNTL registers are reset. QEA/QEB signals used for index match have swap and polarity values
applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
3: The selected clock rate should be at least twice the expected maximum quadrature count rate.