Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 155

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X

bit 4 Unimplemented: Read as ‘0’

bit 3 CF: Clock Fail Detect bit

(3)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2-1 Unimplemented: Read as ‘0’

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Requests oscillator switch to selection specified by the NOSC<2:0> bits

0 = Oscillator switch is complete

(1)

(CONTINUED)

Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70580) in the

“dsPIC33E/PIC24E Family Reference Manual” (available from the Microchip web site) for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC

mode as a transitional clock source between the two PLL modes.

3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an

actual oscillator failure and trigger an oscillator failure trap.