Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 137
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
8.0 DIRECT MEMORY ACCESS
(DMA)
The DMA controller transfers data between Peripheral
Data registers and Data Space SRAM
In addition, DMA can access the entire data memory
space. The Data Memory Bus Arbiter is utilized when
either the CPU or DMA attempts to access SRAM,
resulting in potential DMA or CPU stalls.
The DMA controller supports 4 independent channels.
Each channel can be configured for transfers to or from
selected peripherals. Some of the peripherals
supported by the DMA controller include:
• ECAN™
• Analog-to-Digital Converter (ADC)
• Serial Peripheral Interface (SPI)
•UART
• Input Capture
• Output Compare
Refer to Table 8-1 for a complete list of supported
peripherals.
FIGURE 8-1: DMA CONTROLLER
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 22. “Direct Memory
Access (DMA)” (DS70348) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
DMAPERIPHERAL
Data Memory
SRAM
(see Figure 4-18)
Arbiter