Datasheet

© 2011 Microchip Technology Inc. DS70143E-page 223
dsPIC30F6011A/6012A/6013A/6014A
APPENDIX A: REVISION HISTORY
Revision A (January 2005)
Original data sheet for dsPIC30F6011A, 6012A, 6013A
and 6014A devices.
Revision B (September 2005)
Revision B of this data sheet reflects these changes:
• 12-Bit ADC allows up to 200 ksps sampling rate
(see Section 19.6 “Selecting the ADC Conver-
sion Clock” and Section 19.7 “ADC Speeds”),
• FRC Oscillator revised to allow tuning in ±0.75%
increments (see Section 20.2.5 “Fast RC Oscil-
lator (FRC)” and Table 20-4).
• Revised electrical characteristics:
- Operating Current (I
DD) (see Ta b le 2 3-5 )
- Idle Current (IIDLE) (see Ta ble 23- 6 )
- Power-Down Current (I
PD) (seeTable 23-7)
- Brown-Out Reset (BOR) (see Table 23-11)
- External Clock Timing Requirements (see
Table 23-14)
- PLL Clock Timing Specification (V
DD = 2.5-
5.5 V) (see Table 23-15)
- PLL Jitter (seeTable 23-16)
- Internal FRC Jitter Accuracy and Drift (see
Table 23-18)
- 12-Bit ADC Module Specifications (see
Table 23-38)
- 12-Bit ADC Conversion Timing Requirements
(see Table 23-39)
Revision C (October 2006)
Revision C of this data sheet reflects these changes:
• BSRAM and SSRAM SFRs added for Data RAM
protection (see Section 3.2.7 “Data Ram Protec-
tion Feature”)
• Added INTTREG register (see Section 5.0
“Interrupts”)
•Revised I
2
C Slave Addresses (see Table 15-1)
• Base Instruction CP1 removed from instruction
set (see Table 21-2)
• Revised electrical characteristics:
- Operating Current (I
DD) (see Ta b le 2 3-5 )
- Idle Current (I
IDLE) (see Tab l e 2 3 -6)
- Power-Down Current (IPD) (seeTable 23-7)
- I/O Pin Input Specifications (see Table 23-8)
- Brown-Out Reset (BOR) (see Table 23-11)
- Watchdog Timer (see Table 23-21)
Revision D (March 2008)
This revision reflects these updates:
• Added FUSE Configuration Register (FICD)
details (see Section 20.8 “Device Configuration
Registers” and Table 20-8)
• Removed erroneous statement regarding genera-
tion of CAN receive errors (see Section 17.4.5
“Receive Errors”)
• Electrical Specifications:
- Resolved TBD values for parameters DO10,
DO16, DO20, and DO26 (see Ta ble 2 3 -9)
- 10-bit High-Speed ADC t
PDU timing parame-
ter (time to stabilize) has been updated from
20 µs typical to 20 µs maximum (see
Table 23-39)
- Parameter OS65 (Internal RC Accuracy) has
been expanded to reflect multiple Min and
Max values for different temperatures (see
Table 23-19)
- Parameter DC12 (RAM Data Retention Volt-
age) has been updated to include a Min value
(see Table 23-4)
- Parameter D134 (Erase/Write Cycle Time)
has been updated to include Min and Max
values and the Typ value has been removed
(see Table 23-12)
- Removed parameters OS62 (Internal FRC
Jitter) and OS64 (Internal FRC Drift) and
Note 2 from AC Characteristics (see
Table 23-18)
- Parameter OS63 (Internal FRC Accuracy)
has been expanded to reflect multiple Min
and Max values for different temperatures
(see Table 23-18)
- Updated I/O Pin characteristics parameters
DI19 and DI29 (see Ta ble 2 3 -8)
- Removed parameters DC27a, DC27b,
DC47a, and DC47b (references to I
DD, 20
MIPs @ 3.3V) in Table 23 -5 and Table 23-6
- Removed parameters CS77 and CS78
(references to T
FACL and TRACL @ 3.3V) in
Table 23-30
- Updated Min and Max values and Conditions
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for parame-
ter SY20 (see Table 23-21)
• Preliminary marking removed from document
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• Additional minor corrections throughout the
document