Datasheet

dsPIC30F6011A/6012A/6013A/6014A
DS70143E-page 20 © 2011 Microchip Technology Inc.
2.3 Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
• DIVF - 16/16 signed fractional divide
• DIV.sd - 32/16 signed divide
• DIV.ud - 32/16 unsigned divide
• DIV.sw - 16/16 signed divide
• DIV.uw - 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion as shown in Ta b l e 2 -2 (REPEAT will execute the tar-
get instruction {operand value + 1} times). The
REPEAT loop count must be setup for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
2.4 DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC30F is a single-cycle instruction flow archi-
tecture; therefore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction
(e.g., ED, EDAC).
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations,
which require no additional data. These instructions are
ADD, SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for ACCA (SATA).
5. Automatic saturation on/off for ACCB (SATB).
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection
(ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2: DIVIDE INSTRUCTIONS
Note: The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Note: For CORCON layout, see Table 3-3.
TABLE 2-1: DSP INSTRUCTIONS
SUMMARY
Instruction
Algebraic
Operation
ACC Write
Back
CLR A = 0 Yes
ED A = (x – y)
2
No
EDAC A = A + (x – y)
2
No
MAC A = A + (x * y) Yes
MAC A = A + x
2
No
MOVSAC No change in A Yes
MPY A = x * y No
MPY A = x
2
No
MPY.N A = – x * y No
MSC A = A – x * y Yes
Instruction Function
DIVF
Signed fractional divide: Wm/Wn → W0; Rem → W1
DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
DIV.sw Signed divide: Wm/Wn → W0; Rem → W1
DIV.uw Unsigned divide: Wm/Wn → W0; Rem → W1