dsPIC30F6011A/6012A/6013A/6014A Data Sheet High-Performance, 16-bit Digital Signal Controllers © 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
dsPIC30F6011A/6012A/6013A/6014A High-Performance, 16-bit Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6011A/6012A/6013A/6014A CMOS Technology: • • • • Low-power, high-speed Flash technology Wide operating voltage range (2.5V to 5.
dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6011A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKI V
dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6012A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS
dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 RG14 CN23/RA7 CN22/RA6 RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RG13 80-Pin TQFP RG15 1 T2CK/RC1 2 T3CK/RC2 3 T4CK/RC3 T5CK/RC4 SCK2/CN8/RG6 4 5 6 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 56 IC4/RD11 IC3/RD10 55 IC2/RD9 IC1
dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 CSCK/RG14 CN23/RA7 CN22/RA6 CSDI/RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CSDO/RG13 80-Pin TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 T4CK/RC3 T5CK/RC4 SCK2/CN8/RG6 4 5 6 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 56 IC4/RD11 IC3/R
dsPIC30F6011A/6012A/6013A/6014A Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 CPU Architecture Overview........................................................................................................................................................ 17 3.0 Memory Organization .............................................................
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 10 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 1.0 Note: DEVICE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A FIGURE 1-1: dsPIC30F6011A/6012A BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 Interrupt Controller 16 Data Latch PSV & Table Data Access 8 24 Control Block Y Data RAM 16 16 Data Latch X Data RAM Address Address Latch Latch 16 16 16 24 24 Address Latch Program Memory (Up to 144 Kbytes) Data EEPROM (Up to 4 Kbytes) AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 AN9/RB9
dsPIC30F6011A/6012A/6013A/6014A FIGURE 1-2: dsPIC30F6013A/6014A BLOCK DIAGRAM Y Data Bus 16 16 16 Interrupt Controller Data Latch PSV & Table Data Access 24 Control Block 8 16 Data Latch X Data RAM Y Data RAM 16 Address Address Latch Latch 16 16 16 24 24 Address Latch Data EEPROM (Up to 4 Kbytes) 16 PORTA X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Program Memory (Up to 144 Kbytes) CN22/RA6 CN23/RA7 VREF-/RA9 VREF+/RA10 INT1/RA12 INT2/RA13 INT3/
dsPIC30F6011A/6012A/6013A/6014A Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN15 I Analog Analog input channels.
dsPIC30F6011A/6012A/6013A/6014A TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PGD PGC I/O I ST ST In-Circuit Serial Programming™ data input/output pin. In-Circuit Serial Programming clock input pin. RA6-RA7 RA9-RA10 RA12-RA15 I/O I/O I/O ST ST ST PORTA is a bidirectional I/O port. RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4 RC13-RC15 I/O I/O ST ST PORTC is a bidirectional I/O port.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 16 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 2.0 Note: 2.1 CPU ARCHITECTURE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC30F6011A/6012A/6013A/6014A 2.3 Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: • • • • • DIVF - 16/16 signed fractional divide DIV.sd - 32/16 signed divide DIV.ud - 32/16 unsigned divide DIV.sw - 16/16 signed divide DIV.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In 40 Saturate S a Round t 16 u Logic r a t e Adder Negate 40 40 40 Barrel Shifter 16 X Data Bus 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 2.4.1 MULTIPLIER The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits.
dsPIC30F6011A/6012A/6013A/6014A The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred.
dsPIC30F6011A/6012A/6013A/6014A 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
dsPIC30F6011A/6012A/6013A/6014A 3.0 Note: 3.1 MEMORY ORGANIZATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F6011A/ 6013A Reset – GOTO Instruction Reset – Target Address FIGURE 3-2: 000000 000002 000004 PROGRAM SPACE MEMORY MAP FOR dsPIC30F6012A/ 6014A Reset – GOTO Instruction Reset – Target Address Vector Tables Vector Tables Alternate Vector Table User Flash Program Memory (44K instructions) Reserved (Read ‘0’s) Data EEPROM (2 Kbytes) Interrupt Vector Table 00007E 000080 000084 0000FE 000100 User Memory Space User Memory
dsPIC30F6011A/6012A/6013A/6014A TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> Instruction Access User TBLRD/TBLWT User (TBLPAG<7> = 0) TBLPAG<7:0> Data EA<15:0> TBLRD/TBLWT Configuration (TBLPAG<7> = 1) TBLPAG<7:0> Data EA<15:0> Program Space Visibility User FIGURE 3-3: <0> PC<22:1> 0 0 PSVPAG<7:0> 0 Data EA<14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter
dsPIC30F6011A/6012A/6013A/6014A 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS A set of table instructions are provided to move byte or word sized data to and from program space. 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 TBLRDH.B (Wn<0> = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Program Space 0x000100 Data Space 0x0000 EA<15> = 0 PSVPAG(1) 0x02 8 15 Data 16 Space 15 EA EA<15> = 1 0x8000 15 Address Concatenation 23 23 15 0 0x010000 Upper Half of Data Space is Mapped into Program Space 0xFFFF 0x017FFF BSET MOV MOV MOV CORCON,#2 #0x02, W0 W0, PSVPAG 0x8000, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read Note 1: PSVPAG
dsPIC30F6011A/6012A/6013A/6014A 3.2 Data Address Space The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. 3.2.1 DATA SPACE MEMORY MAP The data space memory is split into two blocks, X and Y data space.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-7: DATA SPACE MEMORY MAP FOR dsPIC30F6011A/6013A MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 6 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 0x1FFF 0x1FFE Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70143E-page 32 0xFFFE © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-8: DATA SPACE MEMORY MAP FOR dsPIC30F6012A/6014A MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x07FE 0x0800 X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 0x1FFF 0x1FFE 8 Kbyte Near Data Space Y Data RAM (Y) 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE X SPACE FIGURE 3-9: UNUSED UNUSED X SPACE Y SPACE X SPACE (Y SPACE) UNUSED Non-MAC Class Ops (Read) MAC Class Ops (Read) Indirect EA from any W Indirect EA from W10, W11 Indirect EA from W8, W9 TABLE 3-2: EFFECT OF INVALID MEMORY ACCESSES Attempted Operation Data Returned EA = an unimplemented address 0x0000(1) W8 or W9 used to access Y data space in a MAC instruction 0x0000
dsPIC30F6011A/6012A/6013A/6014A All word accesses must be aligned to an even address. Misaligned word data fetches are not supported so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the instruction will be executed but the write will not occur.
dsPIC30F6011A/6012A/6013A/6014A 3.2.7 DATA RAM PROTECTION FEATURE The dsPIC30F6011A/6012A/6013A/6014A devices support data RAM protection features which enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled.
© 2011 Microchip Technology Inc.
DS70143E-page 38 0050 0052 0750 0752 XBREV DISICNT BSRAM SSRAM — — — BREN — — — YMODEN — — XMODEN OB OA Bit 14 — — — — SA Bit 13 — — — US SB Bit 12 — — EDT OAB Bit 11 DL1 DA Bit 9 — — — — BWM<3:0> DL2 SAB Bit 10 — — YE<15:1> YS<15:1> XE<15:1> XS<15:1> DL0 DC Bit 8 — — — — RA Bit 4 — — — — SATDW ACCSAT IPL0 Bit 5 YWM<3:0> SATB IPL1 Bit 6 DISICNT<13:0> XB<14:0> SATA IPL2 Bit 7 u = uninitialized bit; — = unimplemented bit, read as ‘
dsPIC30F6011A/6012A/6013A/6014A 4.0 Note: ADDRESS GENERATOR UNITS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A 4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.
dsPIC30F6011A/6012A/6013A/6014A 4.2.1 START AND END ADDRESS 4.2.2 The Modulo Addressing scheme requires that a starting and an ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT, YMODEND (see Table 3-3). Note: Y space Modulo Addressing EA calculations assume word sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified.
dsPIC30F6011A/6012A/6013A/6014A 4.2.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 1
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 44 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 5.0 Note: INTERRUPTS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A 5.1 Interrupt Priority The user-assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user. Note: The user-assignable priority levels start at 0 as the lowest priority and level 7 as the highest priority.
dsPIC30F6011A/6012A/6013A/6014A 5.2 Reset Sequence A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location immediately followed by the address target for the GOTO instruction.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 5-1: Decreasing Priority • Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address • Executing instructions after modifying the PC to point to unimplemented program memory addresses.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 5-2: Stack Grows Towards Higher Address 0x0000 15 INTERRUPT STACK FRAME 0 PC<15:0> SRL IPL3 PC<22:16> W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH: [W15++] Note 1: The user can always lower the priority level by writing a new value into SR. The Interrupt Service Routine must clear the interrupt flag bits in the IFSx register before lowering the processor interrupt priority, in order to avoid recursive interrupts.
Bit 15 0086 0088 008C 008E 0090 0094 0096 0098 IFS1 DS70143E-page 50 IFS2 IEC0 IEC1 IEC2 IPC0 IPC1 IPC2 — 00A0 00A2 00A4 00A6 00A8 IPC6 IPC7 IPC8 IPC9 IPC10 INTTREG 00B0 Legend: Note 1: 2: — 009E IPC5 — — — — IC5IE CNIP<2:0> ADIP<2:0> T31P<2:0> T1IP<2:0> — IC4IE SI2CIE — IC4IF SI2CIF — — — OC8IP<2:0> IC6IP<2:0> — IC3IF — — — — IC3IE NVMIE INT2IP<2:0> C1IP<2:0> — — Bit 12 NVMIF OC3IP<2:0> MI2CIE — IC5IF MI2CIF — — — DISI Bit 13 Bit
dsPIC30F6011A/6012A/6013A/6014A 6.0 Note: FLASH PROGRAM MEMORY 6.2 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A 6.4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. Each panel consists of 128 rows or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary.
dsPIC30F6011A/6012A/6013A/6014A 6.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 6.6.1 4. 5.
dsPIC30F6011A/6012A/6013A/6014A 6.6.3 LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer.
0766 NVMKEY — — WR Bit 15 — — WREN Bit 14 — — WRERR Bit 13 NVM REGISTER MAP(1) — — — — — — — — — Bit 12 Bit 11 Bit 10 — — — Bit 9 — Bit 7 — — NVMADR<15:0> TWRI Bit 8 Bit 6 u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0764 NVMADRU Legend: Note 1: 0760 0762 NVMADR Addr.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 56 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 7.0 Note: DATA EEPROM MEMORY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A 7.2 7.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register. Setting the WR bit initiates the erase as shown in Example 7-2.
dsPIC30F6011A/6012A/6013A/6014A 7.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase data EEPROM word. a) Select word, data EEPROM erase and set WREN bit in NVMCON register. b) Write address of word to be erased into NVMADR. c) Enable NVM interrupt (optional). d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit. This will begin erase cycle. g) Either poll NVMIF bit or wait for NVMIF interrupt.
dsPIC30F6011A/6012A/6013A/6014A 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: 7.
dsPIC30F6011A/6012A/6013A/6014A 8.0 Note: I/O PORTS Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
dsPIC30F6011A/6012A/6013A/6014A 8.2 Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. FIGURE 8-2: When reading the Port register, all pins configured as analog input channels will read as cleared (a low level).
© 2011 Microchip Technology Inc.
LATD — — — — — — Bit 14 Bit 15 — — — Bit 13 — — — Bit 12 Bit 10 Bit 9 LATD11 RD11 LATD10 RD10 LATD9 RD9 TRISD11 TRISD10 TRISD9 Bit 11 DS70143E-page 64 LATD14 LATD13 LATD12 RD12 LATD11 RD11 LATD10 RD10 LATD9 RD9 LATD8 RD8 TRISD8 Bit 8 LATD7 RD7 TRISD7 Bit 7 02DE 02E0 02E2 TRISF PORTF LATF — — — Bit 15 — — — Bit 14 — — — Bit 13 — — — Bit 12 — — — Bit 11 — — — Bit 10 — — — Bit 9 — — — Bit 8 — — — Bit 7 PORTF REGISTER MAP FOR dsPI
02E8 LATG Bit 14 Bit 13 Bit 12 LATG15 RG15 LATG14 RG14 LATG13 RG13 LATG12 RG12 TRISG15 TRISG14 TRISG13 TRISG12 Bit 15 — — — — — — Bit 10 Bit 11 LATG9 RG9 TRISG9 Bit 9 LATG8 RG8 TRISG8 Bit 8 LATG7 RG7 TRISG7 Bit 7 LATG6 RG6 TRISG6 Bit 6 — — — Bit 5 PORTG REGISTER MAP FOR dsPIC30F6011A/6012A/6013A/6014A(1) u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6011A/6012A/6013A/6014A 8.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor, in response to a change of state on selected input pins. This module is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. There are up to 24 external signals (CN0 through CN23) that may be selected (enabled) for generating an interrupt request on a change of state.
dsPIC30F6011A/6012A/6013A/6014A 9.0 Note: TIMER1 MODULE These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). Figure 9-1 presents a block diagram of the 16-bit Timer1 module.
dsPIC30F6011A/6012A/6013A/6014A 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0). When the CPU goes into the Idle mode, the timer will stop incrementing unless TSIDL = 0.
dsPIC30F6011A/6012A/6013A/6014A 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal, up to the value specified in the Period register and is then reset to ‘0’. The TSYNC bit must be asserted to a logic ‘0’ (Asynchronous mode) for correct operation. Enabling the LPOSCEN bit (OSCCON<1>) will disable the normal Timer and Counter modes and enable a timer carry-out wake-up event.
TSIDL — — — — — Bit 7 Bit 6 — TGATE Period Register 1 Timer1 Register Bit 8 u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. — Bit 9 Legend: Note 1: TON Bit 10 0104 Bit 11 T1CON Bit 12 0100 Bit 13 0102 Bit 14 PR1 Bit 15 TIMER1 REGISTER MAP(1) TMR1 Addr.
dsPIC30F6011A/6012A/6013A/6014A 10.0 Note: TIMER2/3 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the most significant word (msw) of the 32-bit timer.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 16 Read TMR2 16 Reset ADC Event Trigger Equal TMR3 TMR2 MSB LSB Comparator x 32 PR3 T3IF Event Flag Sync PR2 0 1 D Q CK TGATE (T2CON<6>) TCS TGATE TGATE (T2CON<6>) Q T2CK Note: 1x Gate Sync 01 TCY 00 TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 Timer configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Reset T2IF Event Flag Comparator x 16 TMR2 Sync 0 1 Q D Q CK TGATE TCS TGATE TGATE T2CK FIGURE 10-3: 1x Gate Sync 01 TCY 00 TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal Reset T3IF Event Flag Comparator x 16 TMR3 0 1 Q D Q CK T3CK TCS TGATE TGATE TGATE Sync 1x 01 TCY © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 10.1 Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).
— — — — u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 76 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 11.0 Note: TIMER4/5 MODULE • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral modules, such as input capture and output compare This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Reset Comparator x 16 TMR4 Sync 0 T4IF Event Flag Q D Q CK TGATE TCS TGATE 1 TGATE T4CK 1x FIGURE 11-3: Gate Sync 01 TCY 00 TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 16-BIT TIMER5 BLOCK DIAGRAM PR5 ADC Event Trigger Equal Reset TMR5 0 1 Q D Q CK TGATE T5CK TGATE TCS TGATE T5IF Event Flag Comparator x 16 Sync 1x 01 TCY Note: TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 In the dsPIC30F
0118 011A 011C 011E 0120 TMR5 PR4 PR5 T4CON T5CON TON TON Bit 15 — — Bit 14 TSIDL TSIDL Bit 13 — — Bit 12 — — Bit 11 TIMER4/5 REGISTER MAP(1) Bit 9 Bit 7 Bit 6 Timer 4 Register Bit 8 Bit 5 — — — — — — — — TGATE TGATE Period Register 5 Period Register 4 Timer 5 Register TCKPS1 TCKPS1 Timer 5 Holding Register (for 32-bit operations only) Bit 10 u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for des
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 80 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 12.0 INPUT CAPTURE MODULE Note: These Operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain up to 8 capture channels (i.e., the maximum value of N is 8). This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
dsPIC30F6011A/6012A/6013A/6014A 12.1.2 CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO.
© 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 84 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 13.0 Note: OUTPUT COMPARE MODULE The key operational features of the output compare module include: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6011A/6012A/6013A/6014A 13.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.
dsPIC30F6011A/6012A/6013A/6014A 13.4.2 PWM PERIOD When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1.
dsPIC30F6011A/6012A/6013A/6014A 13.5 Output Compare Operation During CPU Sleep Mode When the CPU enters Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state. For example, if the pin was high when the CPU entered the Sleep state, the pin will remain high. Likewise, if the pin was low when the CPU entered the Sleep state, the pin will remain low.
0196 © 2011 Microchip Technology Inc. 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC 01AE u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 90 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 14.0 Note: SPI™ MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Serial Peripheral Interface (SPI™) module is a synchronous serial interface.
dsPIC30F6011A/6012A/6013A/6014A 14.2 Framed SPI Support pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). The frame pulse is an active-high pulse for a single SPI clock cycle. When frame synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock. The module supports a basic framed SPI protocol in Master or Slave mode.
dsPIC30F6011A/6012A/6013A/6014A 14.3 Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven. Also, the SPI module is resynchronized, and all counters/control circuitry are reset.
Bit 7 DS70143E-page 94 0228 022A SPI2BUF — SPIFSD SPISIDL — — — SPIEN Bit 15 FRMEN — Bit 14 SPIFSD SPISIDL Bit 13 — — Bit 12 SPI2 REGISTER MAP(1) FRMEN — — — Bit 10 DISSDO MODE16 — Bit 11 DISSDO MODE16 — — CKE — SSEN CKP SPIROV Bit 6 CKE — Bit 8 SSEN — Bit 7 CKP SPIROV Bit 6 Transmit and Receive Buffer SMP — Bit 9 Transmit and Receive Buffer SMP — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of
dsPIC30F6011A/6012A/6013A/6014A 15.0 Note: I2C™ MODULE 15.1.1 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6011A/6012A/6013A/6014A FIGURE 15-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV SCL Read Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect I2CSTAT Write Control Logic Start, Restart, Stop bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70143E-page 96 Write I2CBRG FCY Read © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 15.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 Least Significant bits of the I2CADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
dsPIC30F6011A/6012A/6013A/6014A 15.4.1 10-BIT MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 15.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 15.
dsPIC30F6011A/6012A/6013A/6014A 15.7 Interrupts The I2C module generates two interrupt flags, MI2CIF (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Interrupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. 15.8 Slope Control The I2C standard requires slope control on the SDA and SCL signals for Fast mode (400 kHz).
dsPIC30F6011A/6012A/6013A/6014A 15.12.3 BAUD RATE GENERATOR 2 In I C Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high. As per the I2C standard, FSCK may be 100 kHz or 400 kHz. However, the user can specify any baud rate up to 1 MHz.
— — — — — — — I2CSIDL SCLREL IPMIEN — — — — BCL A10M — — — Bit 10 GCSTAT DISSLW — — — Bit 9 ADD10 SMEN — — Bit 8 IWCOL GCEN Bit 7 — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 102 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE Note: 16.1 The key features of the UART module are: • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6011A/6012A/6013A/6014A FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE Write UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Load RSR to Buffer Receive Shift Register (UxRSR) Control Signals FERR UxRX 8-9 PERR LPBACK From UxTX 1 16 Divider 16x Baud Clock from Baud Rate Generator UxRXIF
dsPIC30F6011A/6012A/6013A/6014A 16.2 16.2.1 Enabling and Setting Up UART ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input respectively, overriding the TRIS and LATCH register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘1’ when no transmission is taking place. 16.2.2 16.3 16.3.
dsPIC30F6011A/6012A/6013A/6014A 16.3.4 TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit: 1. 2. If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty word.
dsPIC30F6011A/6012A/6013A/6014A 16.5.2 FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’, otherwise FERR will be set. The read only FERR bit is buffered along with the received data. It is cleared on any Reset. 16.5.3 PARITY ERROR (PERR) The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected.
dsPIC30F6011A/6012A/6013A/6014A 16.9 Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. 16.10.
— © 2011 Microchip Technology Inc. — U2STA — WAKE — — — — — — UTX8 LPBACK Bit 6 Baud Rate Generator Prescaler URX8 u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 110 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 17.0 Note: 17.1 CAN MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). Overview The CAN bus module consists of a protocol engine and message buffering/control.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 BUFFERS Acceptance Filter RXF2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF MESSAGE TXB1 MSGREQ TXABT TXLARB TXERR MTXBUFF TXB0 A c c e p t R X B 0 Message Queue Control Transmit Byte Sequencer Acceptance Mask RXM0 Acceptance Filter RXF3 Acceptance Filter RXF0 Acceptance Filter RXF4 Acceptance Filter RXF1 Acceptance Filter RXF5 Iden
dsPIC30F6011A/6012A/6013A/6014A 17.3 Modes of Operation The CAN module can operate in one of several Operation modes selected by the user. These modes include: • • • • • • Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Loopback Mode Error Recognition Mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>).
dsPIC30F6011A/6012A/6013A/6014A 17.4 17.4.1 Message Reception RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine.
dsPIC30F6011A/6012A/6013A/6014A • Receive Error Interrupts: A receive error interrupt will be indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt status register, CiINTF. - Invalid Message Received: If any type of error occurred during reception of the last message, an error will be indicated by the IVRIF bit. - Receiver Overrun: The RXnOVR bit indicates that an overrun condition occurred.
dsPIC30F6011A/6012A/6013A/6014A 17.5.6 17.6 TRANSMIT INTERRUPTS Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
dsPIC30F6011A/6012A/6013A/6014A 17.6.2 PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64, in addition to a fixed divide-by-2 for clock generation. The time quantum (TQ) is a fixed unit of time derived from the oscillator period, and is given by Equation 17-1. Note: FCAN must not exceed 30 MHz. If CANCKS = 0, then FCY must not exceed 7.5 MHz. EQUATION 17-1: TIME QUANTUM FOR CLOCK GENERATION TQ = 2 (BRP<5:0> + 1) / FCAN 17.6.
— C1RXF0EIDH 0302 DS70143E-page 118 — — — — — — — — — — — — — — — — — — — — Receive Acceptance Mask 1 Extended Identifier <5:0> Transmit Buffer 2 Standard Identifier <10:6> C1RXM1EIDL 033C 0340 C1TX2SID 034A 034C 034E 0350 0352 0354 C1TX2B3 C1TX2B4 C1TX2CON C1TX1SID C1TX1EID C1TX1DLC Legend: Note 1: 0348 C1TX2B2 — — — — — — — — — Bit 8 Bit 7 Bit 6 Bit 5 — — — — — — — — — — — — — — — — — — — — — — — — TXRTR — — — TXRTR — — — — —
© 2011 Microchip Technology Inc.
DS70143E-page 120 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Receive Acceptance Filter 4 Extended Identifier <17:6> — — — — — — — Receive Acceptance Filter 5 Standard Identifier <10:0> Receive Acceptance Filter 5 Extended Identifier <17:6> — — — — — — — Receive Acceptance Mask 0 Standard Identifier <10:0> — — — — Receive Acceptance Filter 5 Extended Identifier <5:0> — — — Receive Acceptance Filter 3 Extended Identifier <17:6> — — — — — — — Receive Acceptance F
Addr.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 122 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 18.0 Note: 18.1 DATA CONVERTER INTERFACE (DCI) MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6011A/6012A/6013A/6014A FIGURE 18-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate CSCK Generator FSD Word Size Selection bits 16-bit Data Bus Frame Length Selection bits DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO DS70143E-page 124 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 18.3 18.3.1 DCI Module Operation MODULE ENABLE The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Clearing the DCIEN control bit has the effect of resetting the module. In particular, all counters associated with CSCK generation, frame sync, and the DCI buffer control unit are reset. Frame lengths, up to 16 data words, may be selected.
dsPIC30F6011A/6012A/6013A/6014A In the I2S mode, a frame sync signal having a 50% duty cycle is generated. The period of the I2S frame sync signal in CSCK cycles is determined by the word size and frame sync generator control bits. A new I2S data transfer boundary is marked by a high-to-low or a low-to-high transition edge on the COFS pin. 18.3.
dsPIC30F6011A/6012A/6013A/6014A 18.3.7 BIT CLOCK GENERATOR EQUATION 18-2: The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock will be disabled. If the BCG<11:0> bits are set to a nonzero value, the bit clock generator is enabled.
dsPIC30F6011A/6012A/6013A/6014A 18.3.8 SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sampled on the falling edge of the CSCK signal. If the CSCK bit is set, data will be sampled on the rising edge of CSCK.
dsPIC30F6011A/6012A/6013A/6014A 18.3.14 BUFFER LENGTH CONTROL The amount of data that is buffered between interrupts is determined by the buffer length (BLEN<1:0>) control bits in the DCICON1 SFR. The size of the transmit and receive buffers may be varied from 1 to 4 data words using the BLEN control bits. The BLEN control bits are compared to the current value of the DCI buffer control unit address counter.
dsPIC30F6011A/6012A/6013A/6014A 18.3.18 SLOT STATUS BITS The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers. 18.3.
dsPIC30F6011A/6012A/6013A/6014A The 20-bit mode treats each 256-bit AC-Link frame as sixteen, 16-bit time slots. In the 20-bit AC-Link mode, the module operates as if COFSG<3:0> = 1111 and WS<3:0> = 1111. The data alignment for 20-bit data slots is ignored. For example, an entire AC-Link data frame can be transmitted and received in a packed fashion by setting all bits in the TSCON and RSCON SFRs.
DS70143E-page 132 0256 0258 025A 025C 025E — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6011A/6012A/6013A/6014A 19.0 Note: 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC module has six 16-bit registers: • • • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6011A/6012A/6013A/6014A 19.1 ADC Result Buffer The module contains a 16-word dual port read only buffer, called ADCBUF0...ADCBUFF, to buffer the ADC results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data formats. The contents of the sixteen ADC Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software. 19.
dsPIC30F6011A/6012A/6013A/6014A 19.4 Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to four alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit will cause the conversion trigger event after ~11 TAD.
dsPIC30F6011A/6012A/6013A/6014A 19.7 ADC Speeds The dsPIC30F 12-bit ADC specifications permit a maximum of 200 ksps sampling rate. The table below summarizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-bit ADC Conversion Rates Speed Up to 200 ksps(1) TAD Sampling Minimum Time Min 334 ns 1 TAD Rs Max VDD Temperature 2.5 kΩ 4.5V to 5.
dsPIC30F6011A/6012A/6013A/6014A The following figure depicts the recommended circuit for the conversion rates above 100 ksps. The dsPIC30F6014A is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 63 62 61 65 64 VSS 69 68 67 66 1 60 2 59 3 4 58 5 6 56 7 54 8 9 53 57 C2 0.1 μF dsPIC30F6014A AVDD C5 1 μF AVDD C4 0.1 μF AVDD C3 0.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 TAD SAMPLING TIME TSAMP = 1 TAD TSAMP = 1 TAD ADCLK TCONV = 14 TAD TCONV = 14 TAD SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 ADC Acquisition Requirements The analog input model of the 12-bit ADC is shown in Figure 19-4. The total sampling time for the ADC is a function of the internal amplifier settling time and the holding capacitor charge time.
dsPIC30F6011A/6012A/6013A/6014A 19.9 Module Power-down Modes The module has 2 internal Power modes. When the ADON bit is ‘1’, the module is in Active mode; it is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings. In order to return to the Active mode from Off mode, the user must wait for the ADC circuitry to stabilize. 19.10 ADC Operation During CPU Sleep and Idle Modes 19.10.
dsPIC30F6011A/6012A/6013A/6014A 19.13 Configuring Analog Port Pins 19.14 Connection Considerations The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The analog inputs have diodes to VDD and VSS as ESD protection. This requires that the analog input be between VDD and VSS.
© 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 142 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 20.0 Note: SYSTEM INTEGRATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1) LP 32 kHz crystal on SOSCO:SOSCI(2) HS 10 MHz-25 MHz crystal.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 OSC2 Primary Oscillator PLL x4, x8, x16 PLL Lock COSC<2:0> Primary Osc TUN<3:0> 4 NOSC<2:0> Primary Oscillator Stability Detector OSWEN Internal Fast RC Oscillator (FRC) POR Done Oscillator Start-up Timer Clock Secondary Osc Switching and Control Block SOSCO SOSCI 32 kHz LP Oscillator Secondary Oscillator Stability Detector Internal LowPo
dsPIC30F6011A/6012A/6013A/6014A 20.2 Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) b) FOS<2:0> Configuration bits that select one of four oscillator groups, and FPR<4:0> Configuration bits that select the oscillator choices within the primary group. The selection is as shown in Table 20-2.
dsPIC30F6011A/6012A/6013A/6014A 20.2.2 OSCILLATOR START-UP TIMER (OST) In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer is included. It is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out period is designated as TOST. The TOST time is involved every time the oscillator has to restart (i.e., on POR, BOR and wake-up from Sleep).
dsPIC30F6011A/6012A/6013A/6014A 20.2.6 LOW-POWER RC OSCILLATOR (LPRC) The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT and clock monitor circuits. It may also be used to provide a low frequency clock source option for applications where power consumption is critical, and timing accuracy is not required.
dsPIC30F6011A/6012A/6013A/6014A 20.2.8 PROTECTION AGAINST ACCIDENTAL WRITES TO OSCCON A write to the OSCCON register is intentionally made difficult because it controls clock switching and clock scaling. To write to the OSCCON low byte, the following code sequence must be executed without any other instructions in between: Byte Write 0x46 to OSCCON low Byte Write 0x57 to OSCCON low Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction.
dsPIC30F6011A/6012A/6013A/6014A REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-y — R-y R-y U-0 COSC<2:0> R/W-y R/W-y — R/W-y NOSC<2:0> bit 15 bit 8 R/W-0 R/W-0 POST<1:0> R-0 U-0 R/W-0 U-0 R/W-0 R/W-0 LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Values dependent on FOSC R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 1
dsPIC30F6011A/6012A/6013A/6014A REGISTER 20-2: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 TUN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 -4 Unimplemented: Read as ‘0’ bit 3-0 TUN<3:0>: Lower two bits of TUN field.
dsPIC30F6011A/6012A/6013A/6014A REGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/P R/P FCKSM<1:0> U-0 U-0 U-0 — — — R/P R/P R/P FOS<2:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/P R/P R/P R/P R/P FPR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented:
dsPIC30F6011A/6012A/6013A/6014A 20.4 Reset 20.4.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 20-4: VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset DS70143E-page 154 © 2011 Microc
dsPIC30F6011A/6012A/6013A/6014A 20.4.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: • The oscillator circuit has not begun to oscillate.
dsPIC30F6011A/6012A/6013A/6014A Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column.
dsPIC30F6011A/6012A/6013A/6014A 20.5 20.5.1 Watchdog Timer (WDT) WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer, which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the crystal oscillator) fails. 20.5.
dsPIC30F6011A/6012A/6013A/6014A Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The Sleep status bit in RCON register is set upon wake-up. Note: In spite of various delays applied (TPOR, TLOCK and TPWRT), the crystal oscillator (and PLL) may not be active at the end of the time-out (e.g., for low-frequency crystals).
dsPIC30F6011A/6012A/6013A/6014A 20.9 Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state.
Bit 14 Bit 13 Bit 12 T3MD — T2MD T1MD — — — DCIMD NOSC<2:0> — — LVDL<3:0> Bit 8 SWR Bit 6 I2CMD POST<1:0> — — EXTR Bit 7 LOCK — DS70143E-page 160 BKBUG F8000C COE — — — — — — — — — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. These bits are reserved (read as ‘1’ and must be programmed as ‘1’).
dsPIC30F6011A/6012A/6013A/6014A 21.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6011A/6012A/6013A/6014A All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP.
dsPIC30F6011A/6012A/6013A/6014A TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register ∈ {W0..
dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: Base Instr # Assembly Mnemonic 1 ADD 2 3 4 5 6 7 8 INSTRUCTION SET OVERVIEW ADDC AND ASR BCLR BRA BSET BSW DS70143E-page 164 Assembly Syntax Description # of # of Words Cycles Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,
dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: Base Instr # Assembly Mnemonic 9 BTG 10 11 12 13 BTSC BTSS BTST BTSTS INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 BTG Ws,#bit4 Bit Toggle Ws 1 1 None None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BT
dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: Base Instr # Assembly Mnemonic 29 DIV INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of # of Words Cycles Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: Base Instr # Assembly Mnemonic 48 MPY INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: Base Instr # Assembly Mnemonic 66 RRNC INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of # of Words Cycles Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC30F6011A/6012A/6013A/6014A 22.
dsPIC30F6011A/6012A/6013A/6014A 22.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
dsPIC30F6011A/6012A/6013A/6014A 22.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC30F6011A/6012A/6013A/6014A 22.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 22.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
dsPIC30F6011A/6012A/6013A/6014A 23.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below.
dsPIC30F6011A/6012A/6013A/6014A 23.1 DC Characteristics TABLE 23-1: OPERATING MIPS VS. VOLTAGE VDD Range Temp Range Max MIPS dsPIC30F601XA-30I dsPIC30F601XA-20E 4.5-5.5V -40°C to 85°C 30 — 4.5-5.5V -40°C to 125°C — 20 3.0-3.6V -40°C to 85°C 15 — 3.0-3.6V -40°C to 125°C — 10 2.5-3.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units 2.5 — 5.5 V Industrial temperature Extended temperature Conditions Operating Voltage(2) DC10 VDD Supply Voltage DC11 VDD Supply Voltage 3.0 — 5.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC31a 3.1 6 mA 25°C DC31b 3.2 6 mA 85°C 3.3V DC31c 3.1 6 mA 125°C 0.128 MIPS LPRC (512 kHz) DC31e 5.7 9 mA 25°C DC31f 5.5 9 mA 85°C 5V DC31g 5.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IIDLE)(2) DC51a 2.5 5 mA 25°C DC51b 2.6 5 mA 85°C 3.3V DC51c 2.6 5 mA 125°C 0.128 MIPS LPRC (512 kHz) DC51e 5.5 8 mA 25°C DC51f 5.3 8 mA 85°C 5V DC51g 5.2 8 mA 125°C DC50a 6.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Power Down Current (IPD) DC60a 0.5 — μA 25°C DC60b 1 40 μA 85°C DC60c 24 65 μA 125°C DC60e 0.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units — 0.6 V Conditions Output Low Voltage(2) VOL DO10 I/O ports — — — 0.15 V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 5V — — 0.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. LV10 Characteristic(1) Min Typ Max Units LVDL Voltage on VDD transition LVDL = 0000(2) high to low — — — V LVDL = 0001(2) — — — V 0010(2) — — — V LVDL = 0011(2) — — — V LVDL = 0100 2.50 — 2.65 V LVDL = 0101 2.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. BO10 Symbol VBOR Min Typ(1) Max Units BORV = 11(3) — — — V BORV = 10 2.6 — 2.71 V Characteristic BOR Voltage(2) on VDD transition high to low BORV = 01 4.1 — 4.4 V BORV = 00 4.58 — 4.
dsPIC30F6011A/6012A/6013A/6014A 23.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Operating voltage VDD range as described in Table 23-1.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. OS10 Symbol FOSC Characteristic External CLKIN Frequency(2) (External clocks allowed only in EC mode) Oscillator Frequency(2) Min Typ(1) Max Units Conditions DC 4 4 4 — — — — 40 10 10 7.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Characteristic(1) Symbol Min Typ(2) Max Units Conditions OS50 FPLLI PLL Input Frequency Range(2) 4 4 4 4 4 4 5(3) 5(3) 5(3) 4 4 4 — — — — — — — — — — — — 10 10 7.5(4) 10 10 7.5(4) 10 10 7.5(4) 8.33(3) 8.33(3) 7.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-17: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator Mode FOSC (MHz)(1) TCY (μsec)(2) MIPS(3) w/o PLL MIPS(3) w PLL x4 MIPS(3) w PLL x8 MIPS(3) w PLL x16 EC 0.200 20.0 0.05 — — — XT Note 1: 2: 3: 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Assumption: Oscillator Postscaler is divide by 1. Instruction Execution Cycle Time: TCY = 1/MIPS.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-5: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 23-3 for load conditions. TABLE 23-20: CLKOUT AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-6: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out OSC Time-out SY11 SY30 Internal RESET Watchdog Timer RESET SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. DS70143E-page 188 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-7: BAND GAP START-UP TIME CHARACTERISTICS VBGAP 0V Enable Band Gap (see Note) Band Gap Stable SY40 Note: Set LVDEN bit (RCON<12>) or BOREN bit (FBORPOR<7>). TABLE 23-22: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param No. SY40 Note 1: 2: Symbol TBGAP Standard Operating Conditions: 2.5V to 5.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRX Note: Refer to Figure 23-3 for load conditions. TABLE 23-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 Symbol TtxH TtxL TtxP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Conditions Synchronous, no prescaler 0.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure 23-3 for load conditions. TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Para m No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-12: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO HIGH-Z 70 CS50 LSb MSb CS30 CSDI MSb IN HIGH-Z CS31 LSb IN CS40 CS41 Note: Refer to Figure 23-3 for load conditions. © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-29: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 SDO (CSDO) MSb LSb LSb CS76 CS75 MSb IN SDI (CSDI) CS65 CS66 TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-14: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx BIT14 - - - - - -1 SP31 SDIx MSb IN LSb SP30 LSb IN BIT14 - - - -1 SP40 SP41 Note: Refer to Figure 23-3 for load conditions. TABLE 23-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-15: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 SP40 SDIX LSb BIT14 - - - - - -1 MSb SDOX SP30,SP31 MSb IN BIT14 - - - -1 SP41 LSb IN Note: Refer to Figure 23-3 for load conditions. TABLE 23-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-16: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb BIT14 - - - - - -1 SP51 SP30,SP31 SDIX MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure 23-3 for load conditions. SP40 TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP52 MSb SDOX BIT14 - - - - - -1 LSb SP30,SP31 SDIX MSb IN BIT14 - - - -1 SP51 LSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Stop Condition Start Condition Note: Refer to Figure 23-3 for load conditions. FIGURE 23-19: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure 23-3 for load conditions. © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-35: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) ) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS34 IS31 IS30 IS33 SDA Stop Condition Start Condition FIGURE 23-21: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-36: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) I) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-22: CXTX Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CXRX Pin (input) CA20 TABLE 23-37: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-38: 12-BIT ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply Greater of VDD - 0.3 or 2.7 — Lesser of VDD + 0.3 or 5.5 V VSS - 0.3 — VSS + 0.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-38: 12-BIT ADC MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions AD23A GERR Gain Error(3) +1.25 +1.5 +3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24 EOFF Offset Error -2 -1.5 -1.
dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-23: 12-BIT ADC TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 DONE ADIF ADRES(0) 1 2 3 4 5 6 7 8 9 1 – Software sets ADCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 18. “12-bit A/D Converter” (DS70046) of the ”dsPIC30F Family Reference Manual”. 3 – Software clears ADCON.
dsPIC30F6011A/6012A/6013A/6014A TABLE 23-39: 12-BIT ADC TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions VDD = 3-5.5V (Note 1) Clock Parameters AD50 TAD ADC Clock Period — 334 — ns AD51 tRC ADC Internal RC Oscillator Period 1.2 1.5 1.
dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 212 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
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dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 222 © 2011 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A APPENDIX A: REVISION HISTORY Revision A (January 2005) Original data sheet for dsPIC30F6011A, 6012A, 6013A and 6014A devices. Revision B (September 2005) Revision B of this data sheet reflects these changes: • 12-Bit ADC allows up to 200 ksps sampling rate (see Section 19.6 “Selecting the ADC Conversion Clock” and Section 19.7 “ADC Speeds”), • FRC Oscillator revised to allow tuning in ±0.75% increments (see Section 20.2.5 “Fast RC Oscillator (FRC)” and Table 20-4).
dsPIC30F6011A/6012A/6013A/6014A Revision E (February 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Section 20.0 “System Integration” Added a shaded note on OSCTUN functionality in Section 20.2.5 “Fast RC Oscillator (FRC)”. Section 23.
dsPIC30F6011A/6012A/6013A/6014A INDEX Numerics 12-bit Analog-to-Digital Converter (ADC) Module ............. 133 A AC Characteristics ............................................................ 183 Internal FRC Jitter, Accuracy and Drift ..................... 186 Internal LPRC Accuracy............................................ 186 Load Conditions ........................................................ 183 AC Temperature and Voltage Specifications .................... 183 AC-Link Mode Operation ........
dsPIC30F6011A/6012A/6013A/6014A Alignment (Figure) ...................................................... 35 Effect of Invalid Memory Accesses (Table)................. 34 MCU and DSP (MAC Class) Instructions Example..... 34 Memory Map ............................................................... 31 Memory Map for dsPIC30F6011A/6013A ................... 32 Memory Map for dsPIC30F6012A/6014A ................... 33 Near Data Space ........................................................ 35 Software Stack ...
dsPIC30F6011A/6012A/6013A/6014A I/O Ports .............................................................................. 61 Parallel (PIO) .............................................................. 61 I2C 10-bit Slave Mode Operation ........................................ 97 Reception.................................................................... 98 Transmission............................................................... 98 I2C 7-bit Slave Mode Operation ........................................
dsPIC30F6011A/6012A/6013A/6014A Output Compare Module..................................................... 85 Register Map............................................................... 89 Timing Characteristics .............................................. 193 Timing Requirements ................................................ 193 Output Compare Operation During CPU Idle Mode............ 88 Output Compare Sleep Mode Operation............................. 88 P Packaging Information ......................
dsPIC30F6011A/6012A/6013A/6014A T Table Instruction Operation Summary ................................ 51 Temperature and Voltage Specifications AC ............................................................................. 183 Timer1 Module .................................................................... 67 16-bit Asynchronous Counter Mode ........................... 67 16-bit Synchronous Counter Mode ............................. 67 16-bit Timer Mode..................................................
dsPIC30F6011A/6012A/6013A/6014A Transmit Interrupt...................................................... 106 Transmitting Data...................................................... 105 Transmitting in 8-bit Data Mode ................................ 105 Transmitting in 9-bit Data Mode ................................ 105 UART1 Register Map ................................................ 109 UART2 Register Map ................................................ 109 UART Operation Idle Mode ....................
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