Datasheet

Table Of Contents

dsPIC30F6011/6012/6013/6014

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit

PC, table instruction Effective Address (EA), or data

space EA, when program space is mapped into data

space as defined by Table 3-1. Note that the program

space address is incremented by two between succes-

sive program words in order to provide compatibility

with data space addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) for all accesses other than TBLRD/TBLWT,

which use TBLPAG<7> to determine user or configura-

tion space access. In Table 3-1, Program Space

Address Construction, bit 23 allows access to the

Device ID, the User ID and the Configuration bits.

Otherwise, bit 23 is always clear.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Note: The address map shown in Figure 3-1 and

Figure 3-2 is conceptual, and the actual

memory configuration may vary across

individual devices depending on available

memory.