Datasheet
Table Of Contents
- dsPIC30F6011/6012/6013/6014 High-Performance Digital Signal Controllers
- 1.0 Device Overview
- 2.0 CPU Architecture Overview
- 3.0 Memory Organization
- 3.1 Program Address Space
- FIGURE 3-1: program space memory map FOR dsPIC30F6011/6013
- FIGURE 3-2: program space memory map FOR dsPIC30F6012/6014
- TABLE 3-1: Program Space Address Construction
- FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
- 3.1.1 Data Access From Program Memory using Table Instructions
- 3.1.2 Data Access From Program Memory using Program Space Visibility
- 3.2 Data Address Space
- 3.1 Program Address Space
- 4.0 Address Generator Units
- 5.0 Interrupts
- 6.0 Flash Program Memory
- 6.1 In-Circuit Serial Programming (ICSP)
- 6.2 Run-Time Self-Programming (RTSP)
- 6.3 Table Instruction Operation Summary
- 6.4 RTSP Operation
- 6.5 Control Registers
- 6.6 Programming Operations
- 7.0 Data EEPROM Memory
- 8.0 I/O Ports
- 8.1 Parallel I/O (PIO) Ports
- 8.2 Configuring Analog Port Pins
- FIGURE 8-2: Block Diagram of a ShAred PORT Structure
- TABLE 8-1: PORTA Register MAp for dsPIC30F6013/6014
- TABLE 8-2: PORTB Register MAp for dsPIC30F6011/6012/6013/6014
- TABLE 8-3: PORTC Register MAp for dsPIC30F6011/6012
- TABLE 8-4: PORTC Register MAp for dsPIC30F6013/6014
- TABLE 8-5: PORTD Register MAp for dsPIC30F6011/6012
- TABLE 8-6: PORTD Register MAp for dsPIC30F6013/6014
- TABLE 8-7: PORTF Register MAp for dsPIC30F6011/6012
- TABLE 8-8: PORTF Register MAp for dsPIC30F6013/6014
- TABLE 8-9: PORTG Register MAp for dsPIC30F6011/6012/6013/6014
- 8.3 Input Change Notification Module
- TABLE 8-10: Input change notification register map for dsPIC30F6011/6012 (Bits 15-8)
- TABLE 8-11: Input Change notification register map FOR dsPIC30F6011/6012 (Bits 7-0)
- TABLE 8-12: Input change notification register map for dsPIC30F6013/6014 (Bits 15-8)
- TABLE 8-13: Input Change notification register map FOR dsPIC30F6013/6014 (Bits 7-0)
- 9.0 Timer1 Module
- 10.0 Timer2/3 Module
- 11.0 Timer4/5 Module
- 12.0 Input Capture Module
- 13.0 Output Compare Module
- FIGURE 13-1: Output Compare Mode Block DiagrAm
- 13.1 Timer2 and Timer3 Selection Mode
- 13.2 Simple Output Compare Match Mode
- 13.3 Dual Output Compare Match Mode
- 13.4 Simple PWM Mode
- 13.5 Output Compare Operation During CPU Sleep Mode
- 13.6 Output Compare Operation During CPU Idle Mode
- 13.7 Output Compare Interrupts
- 14.0 SPI Module
- 15.0 I2C Module
- 15.1 Operating Function Description
- 15.2 I2C Module Addresses
- 15.3 I2C 7-bit Slave Mode Operation
- 15.4 I2C 10-bit Slave Mode Operation
- 15.5 Automatic Clock Stretch
- 15.6 Software Controlled Clock Stretching (STREN = 1)
- 15.7 Interrupts
- 15.8 Slope Control
- 15.9 IPMI Support
- 15.10 General Call Address Support
- 15.11 I2C Master Support
- 15.12 I2C Master Operation
- 15.13 I2C Module Operation During CPU Sleep and Idle Modes
- 16.0 Universal Asynchronous Receiver Transmitter (UART) Module
- 17.0 CAN Module
- 18.0 Data Converter Interface (DCI) Module
- 18.1 Module Introduction
- 18.2 Module I/O Pins
- 18.3 DCI Module Operation
- 18.3.1 MODULE ENABLE
- 18.3.2 Word Size Selection Bits
- 18.3.3 Frame SYNC GEnerator
- 18.3.4 Frame Sync Mode Control Bits
- 18.3.5 Master frame sync Operation
- 18.3.6 Slave Frame Sync Operation
- 18.3.7 Bit Clock Generator
- 18.3.8 Sample Clock Edge control Bit
- 18.3.9 Data Justification Control bit
- 18.3.10 Transmit Slot Enable Bits
- 18.3.11 Receive Slot Enable Bits
- 18.3.12 Slot Enable Bits Operation with FRame SYNC
- 18.3.13 Synchronous data transfers
- 18.3.14 Buffer Length Control
- 18.3.15 Buffer Alignment With Data Frames
- 18.3.16 Transmit STATUS BITS
- 18.3.17 RECEIVE STATUS bits
- 18.3.18 SLOT Status Bits
- 18.3.19 CSDO Mode Bit
- 18.3.20 Digital Loopback mode
- 18.3.21 Underflow Mode Control Bit
- 18.4 DCI Module Interrupts
- 18.5 DCI Module Operation During CPU Sleep and Idle Modes
- 18.6 AC-Link Mode Operation
- 18.7 I2S Mode Operation
- 19.0 12-bit Analog-to-Digital Converter (A/D) Module
- FIGURE 19-1: 12-bit ADC Functional Block Diagram
- 19.1 ADC Result Buffer
- 19.2 Conversion Operation
- 19.3 Selecting the Conversion Sequence
- 19.4 Programming the Start of Conversion Trigger
- 19.5 Aborting a Conversion
- 19.6 Selecting the ADC Conversion Clock
- 19.7 ADC Speeds
- 19.8 A/D Acquisition Requirements
- 19.9 Module Power-down Modes
- 19.10 ADC Operation During CPU Sleep and Idle Modes
- 19.11 Effects of a Reset
- 19.12 Output Formats
- 19.13 Configuring Analog Port Pins
- 19.14 Connection Considerations
- 20.0 System Integration
- 20.1 Oscillator System Overview
- 20.2 Oscillator Configurations
- 20.3 Reset
- FIGURE 20-2: Reset SYSTEM BLOCK DIAGRAM
- 20.3.1 POR: Power-ON reset
- FIGURE 20-3: Time-out Sequence on Power-up (MCLR Tied to Vdd)
- FIGURE 20-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1
- FIGURE 20-5: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2
- 20.3.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled)
- 20.3.1.2 Operating without FSCM and PWRT
- 20.3.2 BOR: Programmable Brown-out reset
- 20.4 Watchdog Timer (WDT)
- 20.5 Low-Voltage Detect
- 20.6 Power Saving Modes
- 20.7 Device Configuration Registers
- 20.8 Peripheral Module Disable (PMD) Registers
- 20.9 In-Circuit Debugger
- 21.0 Instruction Set Summary
- 22.0 Development Support
- 22.1 MPLAB Integrated Development Environment Software
- 22.2 MPASM Assembler
- 22.3 MPLAB C18 and MPLAB C30 C Compilers
- 22.4 MPLINK Object Linker/ MPLIB Object Librarian
- 22.5 MPLAB ASM30 Assembler, Linker and Librarian
- 22.6 MPLAB SIM Software Simulator
- 22.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 22.8 MPLAB REAL ICE In-Circuit Emulator System
- 22.9 MPLAB ICD 2 In-Circuit Debugger
- 22.10 MPLAB PM3 Device Programmer
- 22.11 PICSTART Plus Development Programmer
- 22.12 PICkit 2 Development Programmer
- 22.13 Demonstration, Development and Evaluation Boards
- 23.0 Electrical Characteristics
- 23.1 DC Characteristics
- TABLE 23-1: Operating MIPS vs. Voltage
- TABLE 23-2: Thermal Operating Conditions
- TABLE 23-3: Thermal Packaging Characteristics
- TABLE 23-4: DC Temperature and Voltage specifications
- TABLE 23-5: DC Characteristics: Operating Current (Idd)
- TABLE 23-6: DC Characteristics: Idle Current (iidle)
- TABLE 23-7: DC Characteristics: Power-Down Current (Ipd)
- TABLE 23-8: DC Characteristics: I/O Pin Input Specifications
- TABLE 23-9: DC Characteristics: I/O Pin Output Specifications
- FIGURE 23-1: Low-Voltage Detect Characteristics
- TABLE 23-10: Electrical Characteristics: LVDL
- FIGURE 23-2: Brown-out Reset Characteristics
- TABLE 23-11: Electrical Characteristics: BOR
- TABLE 23-12: DC Characteristics: Program and EEPROM
- 23.2 AC Characteristics and Timing Parameters
- TABLE 23-13: Temperature and Voltage Specifications – AC
- FIGURE 23-3: Load Conditions for Device Timing Specifications
- FIGURE 23-4: External Clock Timing
- TABLE 23-14: External Clock Timing Requirements
- TABLE 23-15: PLL Clock Timing Specifications (Vdd = 2.5 to 5.5V)
- TABLE 23-16: PLL JITTER
- TABLE 23-17: Internal Clock Timing examples
- TABLE 23-18: AC Characteristics: Internal RC Accuracy(2)
- TABLE 23-19: Internal RC Accuracy
- FIGURE 23-5: CLKO and I/O Timing Characteristics
- TABLE 23-20: CLKO and I/O Timing Requirements
- FIGURE 23-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Character...
- TABLE 23-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset...
- FIGURE 23-7: band gap Start-up Time Characteristics
- TABLE 23-22: band gap Start-up Time Requirements
- FIGURE 23-8: Type A, B and C Timer External Clock Timing Characteristics
- TABLE 23-23: TYPE A TIMER (Timer1) External Clock Timing Requirements(1)
- TABLE 23-24: TYPE B TIMER (Timer2 and Timer4) External Clock Timing Requirements(1)
- TABLE 23-25: TYPE C TIMER (Timer3 and Timer5) External Clock Timing Requirements(1)
- FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING Characteristics
- TABLE 23-26: Input Capture timing requirements
- FIGURE 23-10: Output Compare Module (OCx) Timing Characteristics
- TABLE 23-27: Output Compare Module timing requirements
- FIGURE 23-11: OC/PWM Module Timing Characteristics
- TABLE 23-28: Simple OC/PWM MODE Timing Requirements
- FIGURE 23-12: DCI Module (Multichannel, I2S modes) Timing Characteristics
- TABLE 23-29: DCI Module (Multichannel, I2S modes) Timing Requirements
- FIGURE 23-13: DCI Module (AC-link mode) Timing Characteristics
- TABLE 23-30: DCI Module (AC-Link Mode) Timing Requirements
- FIGURE 23-14: SPI Module Master Mode (CKE = 0) Timing Characteristics
- TABLE 23-31: SPI Master mode (cke = 0) Timing requirements
- FIGURE 23-15: SPI Module Master Mode (CKE = 1) Timing Characteristics
- TABLE 23-32: SPI Module Master mode (cke = 1) Timing requirements
- FIGURE 23-16: SPI Module Slave Mode (CKE = 0) Timing Characteristics
- TABLE 23-33: SPI Module Slave mode (cke = 0) Timing requirements
- FIGURE 23-17: SPI Module Slave Mode (CKE = 1) Timing Characteristics
- TABLE 23-34: SPI Module Slave mode (cke = 1) Timing requirements
- FIGURE 23-18: I2C™ Bus Start/Stop Bits Timing Characteristics (Master mode)
- FIGURE 23-19: I2C™ Bus Data Timing Characteristics (Master mode)
- TABLE 23-35: I2C™ Bus Data Timing Requirements (Master Mode)
- FIGURE 23-20: I2C™ Bus Start/Stop Bits Timing Characteristics (slave mode)
- FIGURE 23-21: I2C™ Bus Data Timing Characteristics (slave mode)
- TABLE 23-36: I2C™ Bus Data Timing Requirements (Slave Mode)
- FIGURE 23-22: CAN Module I/O Timing Characteristics
- TABLE 23-37: CAN Module I/O Timing Requirements
- TABLE 23-38: 12-bit aDC Module Specifications
- FIGURE 23-23: 12-Bit A/D Conversion Timing Characteristics (asam = 0, ssrc = 000)
- TABLE 23-39: 12-BIT A/D Conversion TiminG rEQUIREMENTS
- 23.1 DC Characteristics
- 24.0 Packaging Information
- Appendix A: Revision History
- Index
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales and Service

dsPIC30F6011/6012/6013/6014
DS70117F-page 22 © 2006 Microchip Technology Inc.
The SA and SB bits are modified each time data
passes through the adder/subtracter but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation, or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When satu-
ration is not enabled, SA and SB default to bit 39 over-
flow and thus indicate that a catastrophic overflow has
occurred. If the COVTE bit in the INTCON1 register is
set, SA and SB bits will generate an arithmetic warning
trap when saturation is disabled.
The overflow and saturation status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three saturation and overflow
modes:
1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF), or maximally negative 9.31
value (0x8000000000) into the target accumula-
tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erro-
neous data, or unexpected algorithm problems
(e.g., gain calculations).
2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally posi-
tive 1.31 value (0x007FFFFFFF), or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used (so the OA, OB or OAB bits are never
set).
3. Bit 39 Catastrophic Overflow:
The bit 39 overflow status bit from the adder is
used to set the SA or SB bit which remain set
until cleared by the user. No saturation opera-
tion is performed and the accumulator is allowed
to overflow (destroying its sign). If the COVTE
bit in the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
2.4.2.2 Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1. W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
2. [W13] + = 2, Register Indirect with
Post-Increment:
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3 Round Logic
The round logic is a combinational block which per-
forms a conventional (biased) or convergent (unbi-
ased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a 16-
bit, 1.15 data value which is passed to the data space
write saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word (lsw) is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word
(bits 0 through 15 of the accumulator) is between
0x8000 and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 and
0x7FFF, ACCxH is left unchanged. A consequence of
this algorithm is that over a succession of random
rounding operations, the value will tend to be biased
slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb
(bit 16 of the accumulator) of ACCxH is examined. If it
is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not
modified. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write back operation
will function in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.