Datasheet

dsPIC30F6011A/6012A/6013A/6014A
DS70143C-page 218 © 2006 Microchip Technology Inc.
D
Data Accumulators and Adder/Subtractor...........................21
Data Space Write Saturation ......................................23
Overflow and Saturation ............................................. 21
Round Logic................................................................22
Write Back...................................................................22
Data Address Space ...........................................................31
Alignment ....................................................................34
Alignment (Figure) ......................................................35
Effect of Invalid Memory Accesses (Table).................34
MCU and DSP (MAC Class) Instructions Example..... 34
Memory Map ...............................................................31
Memory Map for dsPIC30F6011/6013........................32
Memory Map for dsPIC30F6012/6014........................33
Near Data Space ........................................................35
Software Stack............................................................35
Spaces........................................................................31
Width...........................................................................34
Data Converter Interface (DCI) Module ............................125
Data EEPROM Memory......................................................57
Erasing........................................................................58
Erasing, Block.............................................................58
Erasing, Word .............................................................58
Protection Against Spurious Write ..............................61
Reading.......................................................................57
Write Verify .................................................................61
Writing.........................................................................59
Writing, Block..............................................................60
Writing, Word ..............................................................59
DC Characteristics ............................................................173
BOR ..........................................................................181
Brown-out Reset .......................................................180
I/O Pin Input Specifications....................................... 178
I/O Pin Output Specifications....................................179
Idle Current (I
IDLE) ....................................................176
Low-Voltage Detect...................................................179
LVDL.........................................................................180
Operating Current (I
DD).............................................175
Power-Down Current (I
PD)........................................177
Program and EEPROM.............................................181
DCI Module
Bit Clock Generator...................................................129
Buffer Alignment with Data Frames ..........................131
Buffer Control............................................................125
Buffer Data Alignment...............................................125
Buffer Length Control................................................131
COFS Pin..................................................................125
CSCK Pin..................................................................125
CSDI Pin ...................................................................125
CSDO Mode Bit ........................................................132
CSDO Pin .................................................................125
Data Justification Control Bit.....................................130
Device Frequencies for Common Codec
CSCK Frequencies (Table)...............................129
Digital Loopback Mode ............................................. 132
Enable.......................................................................127
Frame Sync Generator ............................................. 127
Frame Sync Mode Control Bits .................................127
I/O Pins .....................................................................125
Interrupts...................................................................132
Introduction ...............................................................125
Master Frame Sync Operation..................................127
Operation ..................................................................127
Operation During CPU Idle Mode .............................132
Operation During CPU Sleep Mode..........................132
Receive Slot Enable Bits .......................................... 130
Receive Status Bits................................................... 131
Register Map ............................................................ 134
Sample Clock Edge Control Bit ................................ 130
Slave Frame Sync Operation.................................... 128
Slot Enable Bits Operation with Frame Sync............ 130
Slot Status Bits ......................................................... 132
Synchronous Data Transfers.................................... 130
Timing Characteristics
AC-Link Mode................................................... 195
Multichannel, I
2
S Modes................................... 193
Timing Requirements
AC-Link Mode................................................... 195
Multichannel, I
2
S Modes................................... 194
Transmit Slot Enable Bits ......................................... 130
Transmit Status Bits.................................................. 131
Transmit/Receive Shift Register ............................... 125
Underflow Mode Control Bit...................................... 132
Word Size Selection Bits .......................................... 127
Development Support....................................................... 169
Device Configuration
Register Map ............................................................ 159
Device Configuration Registers
FBORPOR................................................................ 157
FGS .......................................................................... 157
FOSC........................................................................ 157
FWDT ....................................................................... 157
Device Overview................................................................... 9
Disabling the UART .......................................................... 105
Divide Support .................................................................... 18
Instructions (Table)..................................................... 18
DSP Engine ........................................................................ 19
Multiplier ..................................................................... 21
Dual Output Compare Match Mode.................................... 88
Continuous Pulse Mode.............................................. 88
Single Pulse Mode...................................................... 88
E
Electrical Characteristics .................................................. 173
AC............................................................................. 182
DC ............................................................................ 173
Enabling and Setting Up UART
Setting Up Data, Parity and Stop Bit Selections....... 105
Enabling the UART........................................................... 105
Equations
ADC Conversion Clock............................................. 137
Baud Rate................................................................. 107
Bit Clock Frequency.................................................. 129
COFSG Period.......................................................... 127
Serial Clock Rate...................................................... 100
Time Quantum for Clock Generation........................ 117
Errata .................................................................................... 8
External Clock Timing Characteristics
Type A, B and C Timer ............................................. 189
External Clock Timing Requirements ............................... 183
Type A Timer ............................................................ 189
Type B Timer ............................................................ 190
Type C Timer............................................................ 190
External Interrupt Requests ................................................ 49