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Table Of Contents

High-Performance Modified RISC CPU:
DSP Features:
Peripheral Features:
Analog Features:
Special Microcontroller Features:
CMOS Technology:
dsPIC30F6011A/6012A/6013A/6014A Controller Families
Pin Diagrams
Pin Diagrams (Continued)
Pin Diagrams (Continued)
Pin Diagrams (Continued)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- FIGURE 1-1: dsPIC30F6011A/6012A Block Diagram
- FIGURE 1-2: dsPIC30F6013A/6014A Block Diagram
- TABLE 1-1: PINOUT I/O DESCRIPTIONS
2.0 CPU Architecture Overview
- 2.1 Core Overview
- 2.2 Programmer’s Model
- 2.3 Divide Support
- 2.4 DSP Engine
3.0 Memory Organization
- 3.1 Program Address Space
- 3.2 Data Address Space
4.0 Address Generator Units
- 4.1 Instruction Addressing Modes
- 4.2 Modulo Addressing
- 4.3 Bit-Reversed Addressing
  - 4.3.1 Bit-Reversed Addressing Implementation
5.0 Interrupts
- 5.1 Interrupt Priority
  - TABLE 5-1: Interrupt Vector Table
- 5.2 Reset Sequence
  - 5.2.1 Reset Sources
- 5.3 Traps
  - 5.3.1 Trap Sources
  - 5.3.2 Hard and Soft Traps
    - FIGURE 5-1: Trap VECTORS
- 5.4 Interrupt Sequence
  - FIGURE 5-2: INTERRUPT STACK FRAME
- 5.5 Alternate Vector Table
- 5.6 Fast Context Saving
- 5.7 External Interrupt Requests
- 5.8 Wake-up from Sleep and Idle
  - TABLE 5-2: Interrupt Controller Register Map(1)
6.0 Flash Program Memory
- 6.1 In-Circuit Serial Programming (ICSP)
- 6.2 Run-Time Self-Programming (RTSP)
- 6.3 Table Instruction Operation Summary
  - FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS
- 6.4 RTSP Operation
- 6.5 Control Registers
- 6.6 Programming Operations
7.0 Data EEPROM Memory
- 7.1 Reading the Data EEPROM
  - EXAMPLE 7-1: Data EEPROM Read
- 7.2 Erasing Data EEPROM
  - 7.2.1 Erasing a block of Data EEPROM
    - EXAMPLE 7-2: Data EEPROM block erase
  - 7.2.2 Erasing a Word of Data EEPROM
    - EXAMPLE 7-3: Data EEPROM Word erase
- 7.3 Writing to the Data EEPROM
  - 7.3.1 Writing a Word of Data EEPROM
    - EXAMPLE 7-4: Data EEPROM Word Write
  - 7.3.2 Writing a block of Data EEPROM
    - EXAMPLE 7-5: data eeprom block write
- 7.4 Write Verify
- 7.5 Protection Against Spurious Write
8.0 I/O Ports
- 8.1 Parallel I/O (PIO) Ports
  - FIGURE 8-1: Block Diagram of a Dedicated PORT Structure
- 8.2 Configuring Analog Port Pins
- 8.3 Input Change Notification Module
9.0 Timer1 Module
- FIGURE 9-1: 16-bit Timer1 Module Block diagram
- 9.1 Timer Gate Operation
- 9.2 Timer Prescaler
- 9.3 Timer Operation During Sleep Mode
- 9.4 Timer Interrupt
- 9.5 Real-Time Clock
10.0 Timer2/3 Module
- FIGURE 10-1: 32-bit TIMER2/3 BLOCK DIAGRAM
- FIGURE 10-2: 16-bit TIMER2 BLOCK DIAGRAM
- FIGURE 10-3: 16-bit TIMER3 BLOCK DIAGRAM
- 10.1 Timer Gate Operation
- 10.2 ADC Event Trigger
- 10.3 Timer Prescaler
- 10.4 Timer Operation During Sleep Mode
- 10.5 Timer Interrupt
  - TABLE 10-1: Timer2/3 register map(1)
11.0 Timer4/5 Module
- FIGURE 11-1: 32-bit TIMER4/5 BLOCK DIAGRAM
- FIGURE 11-2: 16-bit TIMER4 BLOCK DIAGRAM
- FIGURE 11-3: 16-bit TIMER5 BLOCK DIAGRAM
- TABLE 11-1: Timer4/5 register map(1)
12.0 Input Capture Module
- 12.1 Simple Capture Event Mode
- 12.2 Input Capture Operation During Sleep and Idle Modes
  - 12.2.1 Input Capture in CPU Sleep Mode
  - 12.2.2 Input Capture in CPU Idle Mode
- 12.3 Input Capture Interrupts
  - TABLE 12-1: Input Capture Register Map(1)
13.0 Output Compare Module
- FIGURE 13-1: Output Compare Mode Block DiagrAm
- 13.1 Timer2 and Timer3 Selection Mode
- 13.2 Simple Output Compare Match Mode
- 13.3 Dual Output Compare Match Mode
  - 13.3.1 Single Pulse Mode
  - 13.3.2 Continuous Pulse Mode
- 13.4 Simple PWM Mode
  - 13.4.1 Input Pin Fault Protection for PWM
  - 13.4.2 PWM Period
    - EQUATION 13-1:
- 13.5 Output Compare Operation During CPU Sleep Mode
- 13.6 Output Compare Operation During CPU Idle Mode
- 13.7 Output Compare Interrupts
  - TABLE 13-1: Output Compare Register Map(1)
14.0 SPI™ Module
- 14.1 Operating Function Description
  - 14.1.1 Word and Byte Communication
  - 14.1.2 SDOx Disable
- 14.2 Framed SPI Support
  - FIGURE 14-1: SPI BLOCK DIAGRAM
  - FIGURE 14-2: SPI Master/Slave Connection
- 14.3 Slave Select Synchronization
- 14.4 SPI Operation During CPU Sleep Mode
- 14.5 SPI Operation During CPU Idle Mode
  - TABLE 14-1: SPI1 Register Map(1)
  - TABLE 14-2: SPI2 Register Map(1)
15.0 I2C™ Module
- 15.1 Operating Function Description
- 15.2 I2C Module Addresses
  - TABLE 15-1: 7-bit I2C™ Slave Addresses supported by dsPIC30F
- 15.3 I2C 7-bit Slave Mode Operation
  - 15.3.1 Slave Transmission
  - 15.3.2 Slave Reception
- 15.4 I2C 10-bit Slave Mode Operation
  - 15.4.1 10-bit Mode Slave Transmission
  - 15.4.2 10-bit Mode Slave Reception
- 15.5 Automatic Clock Stretch
- 15.6 Software Controlled Clock Stretching (STREN = 1)
- 15.7 Interrupts
- 15.8 Slope Control
- 15.9 IPMI Support
- 15.10 General Call Address Support
- 15.11 I2C Master Support
- 15.12 I2C Master Operation
- 15.13 I2C Module Operation During CPU Sleep and Idle Modes
  - 15.13.1 I2C Operation During CPU Sleep MoDE
  - 15.13.2 I2C Operation During CPU Idle Mode
    - TABLE 15-2: I2C™ Register Map(1)
16.0 Universal Asynchronous Receiver Transmitter (UART) Module
- 16.1 UART Module Overview
  - FIGURE 16-1: UART Transmitter Block Diagram
  - FIGURE 16-2: UART Receiver Block Diagram
- 16.2 Enabling and Setting Up UART
- 16.3 Transmitting Data
- 16.4 Receiving Data
- 16.5 Reception Error Handling
- 16.6 Address Detect Mode
- 16.7 Loopback Mode
- 16.8 Baud Rate Generator
- 16.9 Auto-Baud Support
- 16.10 UART Operation During CPU Sleep and Idle Modes
  - 16.10.1 UART Operation During CPU Sleep Mode
  - 16.10.2 UART Operation During CPU Idle Mode
    - TABLE 16-1: UART1 Register Map(1)
    - TABLE 16-2: UART2 Register Map(1)
17.0 CAN Module
- 17.1 Overview
- 17.2 Frame Types
  - FIGURE 17-1: CAN Buffers and Protocol Engine Block Diagram
- 17.3 Modes of Operation
- 17.4 Message Reception
- 17.5 Message Transmission
- 17.6 Baud Rate Setting
18.0 Data Converter Interface (DCI) Module
- 18.1 Module Introduction
- 18.2 Module I/O Pins
- 18.3 DCI Module Operation
- 18.4 DCI Module Interrupts
- 18.5 DCI Module Operation During CPU Sleep and Idle Modes
  - 18.5.1 DCI Module Operation During CPU Sleep Mode
  - 18.5.2 DCI Module Operation During CPU Idle Mode
- 18.6 AC-Link Mode Operation
  - 18.6.1 16-bit AC-link Mode
  - 18.6.2 20-bit AC-Link Mode
- 18.7 I2S Mode Operation
  - 18.7.1 I2S Frame and data word Length Selection
  - 18.7.2 I2S DATA Justification
    - TABLE 18-2: DCI Register Map(1)
19.0 12-bit Analog-to-Digital Converter (ADC) Module
- FIGURE 19-1: 12-bit ADC Functional Block Diagram
- 19.1 ADC Result Buffer
- 19.2 Conversion Operation
- 19.3 Selecting the Conversion Sequence
- 19.4 Programming the Start of Conversion Trigger
- 19.5 Aborting a Conversion
- 19.6 Selecting the ADC Conversion Clock
  - EQUATION 19-1: ADC CONVERSION CLOCK
  - EXAMPLE 19-1: ADC Conversion Clock and Sampling Rate Calculation
- 19.7 ADC Speeds
- 19.8 ADC Acquisition Requirements
  - FIGURE 19-4: 12-bit ADC Analog Input Model
- 19.9 Module Power-down Modes
- 19.10 ADC Operation During CPU Sleep and Idle Modes
  - 19.10.1 ADC Operation During CPU Sleep Mode
  - 19.10.2 ADC Operation During CPU Idle Mode
- 19.11 Effects of a Reset
- 19.12 Output Formats
  - FIGURE 19-5: ADC output data formats
- 19.13 Configuring Analog Port Pins
- 19.14 Connection Considerations
  - TABLE 19-2: ADC Register Map(1)
20.0 System Integration
- 20.1 Oscillator System Overview
  - TABLE 20-1: Oscillator Operating Modes
  - FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM
- 20.2 Oscillator Configurations
- 20.3 Oscillator Control Registers
- 20.4 Reset
  - 20.4.1 POR: Power-ON reset
  - 20.4.2 BOR: Programmable Brown-out reset
- 20.5 Watchdog Timer (WDT)
  - 20.5.1 Watchdog Timer Operation
  - 20.5.2 Enabling and Disabling the WDT
- 20.6 Low-Voltage Detect
- 20.7 Power-Saving Modes
  - 20.7.1 Sleep Mode
  - 20.7.2 Idle Mode
- 20.8 Device Configuration Registers
- 20.9 Peripheral Module Disable (PMD) Registers
- 20.10 In-Circuit Debugger
  - TABLE 20-7: System Integration Register Map For dsPIC30F601XA (1)
  - TABLE 20-8: DEVICE Configuration Register Map(1)
21.0 Instruction Set Summary
- TABLE 21-1: Symbols used in Opcode Descriptions
- TABLE 21-2: Instruction Set OVERVIEW
22.0 Development Support
- 22.1 MPLAB Integrated Development Environment Software
- 22.2 MPLAB C Compilers for Various Device Families
- 22.3 HI-TECH C for Various Device Families
- 22.4 MPASM Assembler
- 22.5 MPLINK Object Linker/ MPLIB Object Librarian
- 22.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 22.7 MPLAB SIM Software Simulator
- 22.8 MPLAB REAL ICE In-Circuit Emulator System
- 22.9 MPLAB ICD 3 In-Circuit Debugger System
- 22.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 22.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 22.12 MPLAB PM3 Device Programmer
- 22.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
23.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 23.1 DC Characteristics
- 23.2 AC Characteristics and Timing Parameters
24.0 Packaging Information
- 24.1 Package Marking Information
Appendix A: Revision History
- Revision A (January 2005)
- Revision B (September 2005)
- Revision C (October 2006)
- Revision D (March 2008)
- Revision E (February 2011)
  - TABLE A-1: Major Section Updates
Index
The Microchip Web Site
Customer Change Notification Service
Customer Support
Reader Response
Product Identification System

© 2011 Microchip Technology Inc. DS70143E-page 205

dsPIC30F6011A/6012A/6013A/6014A

FIGURE 23-20: I

2

C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 23-21: I

2

C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS31

IS34

SCL

SDA

Start

Condition

Stop

Condition

IS30

IS33

IS30

IS31 IS33

IS11

IS10

IS20

IS26

IS25

IS40

IS40

IS45

IS21

SCL

SDA

In

SDA

Out