Datasheet

dsPIC30F6011A/6012A/6013A/6014A
DS70143E-page 196 © 2011 Microchip Technology Inc.
TABLE 23-29: DCI MODULE (MULTICHANNEL, I
2
S MODES) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol Characteristic
(1)
Min Typ
(2)
Max Units Conditions
CS10 Tc
SCKL CSCK Input Low Time
(CSCK pin is an input)
TCY/2 + 20 — — ns
CSCK Output Low Time
(3)
(CSCK pin is an output)
30 — — ns
CS11 Tc
SCKH CSCK Input High Time
(CSCK pin is an input)
TCY/2 + 20 — — ns
CSCK Output High Time
(3)
(CSCK pin is an output)
30 — — ns
CS20 Tc
SCKF CSCK Output Fall Time
(4)
(CSCK pin is an output)
—1025ns
CS21 Tc
SCKR CSCK Output Rise Time
(4)
(CSCK pin is an output)
—1025ns
CS30 TcSDOF CSDO Data Output Fall Time
(4)
—1025ns
CS31 Tc
SDOR CSDO Data Output Rise Time
(4)
—1025ns
CS35 T
DV Clock edge to CSDO data valid — — 10 ns
CS36 TDIV Clock edge to CSDO tri-stated 10 — 20 ns
CS40 T
CSDI Setup time of CSDI data input to
CSCK edge (CSCK pin is input
or output)
20 — — ns
CS41 THCSDI Hold time of CSDI data input to
CSCK edge (CSCK pin is input
or output)
20 — — ns
CS50 TcoFSF COFS Fall Time
(COFS pin is output)
(4)
—1025ns
CS51 TcoFSR COFS Rise Time
(COFS pin is output)
(4)
—1025ns
CS55 Tsco
FS Setup time of COFS data input to
CSCK edge (COFS pin is input)
20 — — ns
CS56 THCOFS Hold time of COFS data input to
CSCK edge (COFS pin is input)
20 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all DCI pins.