Datasheet

dsPIC30F6011A/6012A/6013A/6014A
DS70143E-page 134 © 2011 Microchip Technology Inc.
19.1 ADC Result Buffer
The module contains a 16-word dual port read only buf-
fer, called ADCBUF0...ADCBUFF, to buffer the ADC
results. The RAM is 12 bits wide but the data obtained
is represented in one of four different 16-bit data for-
mats. The contents of the sixteen ADC Result Buffer
registers, ADCBUF0 through ADCBUFF, cannot be
written by user software.
19.2 Conversion Operation
After the ADC module has been configured, the sample
acquisition is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, will terminate acquisition and start
a conversion. When the A/D conversion is complete,
the result is loaded into ADCBUF0...ADCBUFF, and
the DONE bit and the ADC interrupt flag ADIF are set
after the number of samples specified by the SMPI bit.
The ADC module can be configured for different inter-
rupt rates as described in Section 19.3 “Selecting the
Conversion Sequence”.
Use the following steps to perform an Analog-to-Digital
conversion:
1. Configure the ADC module:
a) Configure the analog pins, voltage refer-
ence and digital I/O.
b) Select the ADC input channels.
c) Select the ADC conversion clock.
d) Select the ADC conversion trigger.
e) Turn on the ADC module.
2. Configure ADC interrupt (if required):
a) Clear the ADIF bit.
b) Select the ADC interrupt priority.
3. Start sampling.
4. Wait the required acquisition time.
5. Trigger acquisition end, start conversion:
6. Wait for ADC conversion to complete, by either:
• Waiting for the ADC interrupt, or
• Waiting for the DONE bit to get set.
7. Read ADC result buffer, clear ADIF if required.
19.3 Selecting the Conversion
Sequence
Several groups of control bits select the sequence in
which the ADC connects inputs to the sample/hold
channel, converts a channel, writes the buffer memory
and generates interrupts.
The sequence is controlled by the sampling clocks.
The SMPI bits select the number of acquisition/
conversion sequences that would be performed before
an interrupt occurs. This can vary from 1 sample per
interrupt to 16 samples per interrupt.
The BUFM bit will split the 16-word results buffer into
two 8-word groups. Writing to the 8-word buffers will be
alternated on each interrupt event.
Use of the BUFM bit will depend on how much time is
available for the moving of the buffers after the
interrupt.
If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
the BUFM bit can be ‘0’ and up to 16 conversions (cor-
responding to the 16 input channels) may be done per
interrupt. The processor will have one acquisition and
conversion time to move the sixteen conversions.
If the processor cannot unload the buffer within the
acquisition and conversion time, the BUFM bit should be
‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions will be loaded into 1/2 of the
buffer, following which an interrupt occurs. The next
eight conversions will be loaded into the other 1/2 of the
buffer. The processor will have the entire time between
interrupts to move the eight conversions.
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are
selected for sampling. If the ALTS bit is ‘1’ and
SMPI<3:0> = 0000 on the first sample/convert
sequence, the MUX A inputs are selected and, on the
next acquire/convert sequence, the MUX B inputs are
selected.
The CSCNA bit (ADCON2<10>) will allow the multi-
plexer input to be alternately scanned across a
selected number of analog inputs for the MUX A group.
The inputs are selected by the ADCSSL register. If a
particular bit in the ADCSSL register is ‘1’, the corre-
sponding input is selected. The inputs are always
scanned from lower to higher numbered inputs, starting
after each interrupt. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.