Datasheet

© 2006 Microchip Technology Inc. DS70117F-page 79
dsPIC30F6011/6012/6013/6014
11.0 TIMER4/5 MODULE
This section describes the second 32-bit General Pur-
pose Timer module (Timer4/5) and associated opera-
tional modes. Figure 11-1 depicts the simplified block
diagram of the 32-bit Timer4/5 module. Figure 11-2 and
Figure 11-3 show Timer4/5 configured as two indepen-
dent 16-bit timers, Timer4 and Timer5, respectively.
The Timer4/5 module is similar in operation to the
Timer2/3 module. However, there are some differences
which are as follows:
• The Timer4/5 module does not support the ADC
event trigger feature
• Timer4/5 can not be utilized by other peripheral
modules, such as input capture and
output compare
The operating modes of the Timer4/5 module are deter-
mined by setting the appropriate bit(s) in the 16-bit
T4CON and T5CON SFRs.
For 32-bit timer/counter operation, Timer4 is the lsw
and Timer5 is the msw of the 32-bit timer.
FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
Note: For 32-bit timer operation, T5CON control
bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is gen-
erated with the Timer5 interrupt flag (T5IF)
and the interrupt is enabled with the
Timer5 interrupt enable bit (T5IE).
TMR5
TMR4
T5IF
Equal
Comparator x 32
PR5 PR4
Reset
LSB
MSB
Event Flag
Note: Timer Configuration bit T45 (T4CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T4CON register.
Data Bus<15:0>
TMR5HLD
Read TMR4
Write TMR4
16
16
16
Q
QD
CK
TGATE (T4CON<6>)
(T4CON<6>)
TGATE
0
1
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
T
CY
TCS
1 x
0 1
TGATE
0 0
Gate
T4CK
Sync
Sync