Datasheet

dsPIC30F6011/6012/6013/6014
DS70117F-page 46 © 2006 Microchip Technology Inc.
5.1 Interrupt Priority
The user assignable interrupt priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble within the IPCx regis-
ter(s). Bit 3 of each nibble is not used and is read as a
‘0’. These bits define the priority level assigned to a
particular interrupt by the user.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC device and their associated
vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Low-
Voltage Detect) can be given a priority of 7. The INT0
(External Interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.
TABLE 5-1: INTERRUPT VECTOR TABLE
Note: The user selectable priority levels start at
0 as the lowest priority and level 7 as the
highest priority.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
INT
Number
Vector
Number
Interrupt Source
Highest Natural Order Priority
0 8 INT0 – External Interrupt 0
1 9 IC1 – Input Capture 1
2 10 OC1 – Output Compare 1
3 11 T1 – Timer 1
4 12 IC2 – Input Capture 2
5 13 OC2 – Output Compare 2
6 14 T2 – Timer 2
7 15 T3 – Timer 3
816SPI1
9 17 U1RX – UART1 Receiver
10 18 U1TX – UART1 Transmitter
11 19 ADC – ADC Convert Done
12 20 NVM – NVM Write Complete
13 21 SI2C – I
2
C Slave Interrupt
14 22 MI2C – I
2
C Master Interrupt
15 23 Input Change Interrupt
16 24 INT1 – External Interrupt 1
17 25 IC7 – Input Capture 7
18 26 IC8 – Input Capture 8
19 27 OC3 – Output Compare 3
20 28 OC4 – Output Compare 4
21 29 T4 – Timer 4
22 30 T5 – Timer 5
23 31 INT2 – External Interrupt 2
24 32 U2RX – UART2 Receiver
25 33 U2TX – UART2 Transmitter
26 34 SPI2
27 35 C1 – Combined IRQ for CAN1
28 36 IC3 – Input Capture 3
29 37 IC4 – Input Capture 4
30 38 IC5 – Input Capture 5
31 39 IC6 – Input Capture 6
32 40 OC5 – Output Compare 5
33 41 OC6 – Output Compare 6
34 42 OC7 – Output Compare 7
35 43 OC8 – Output Compare 8
36 44 INT3 – External Interrupt 3
37 45 INT4 – External Interrupt 4
38 46 C2 – Combined IRQ for CAN2
39-40 47-48 Reserved
41 49 DCI – Codec Transfer Done
42 50 LVD – Low-Voltage Detect
43-53 51-61 Reserved
Lowest Natural Order Priority