Datasheet

© 2006 Microchip Technology Inc. DS70117F-page 139
dsPIC30F6011/6012/6013/6014
The following figure depicts the recommended circuit
for the conversion rates above 200 ksps. The
dsPIC30F6014 is shown as an example.
FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC
The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
19.7.1 200 KSPS CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 19-2.
• Connect external V
REF+ and VREF- pins following
the recommended circuit shown in Figure 19-2.
• Set SSRC<2.0> = 111 in the ADCON1 register to
enable the auto convert option.
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register.
• Write the SMPI<3.0> control bits in the ADCON2
register for the desired number of conversions
between interrupts.
• Configure the ADC clock period to be:
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
• Configure the sampling time to be 1 T
AD by
writing: SAMC<4:0> = 00001.
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
AD selection in conjunc-
tion with the guidelines described above allows a con-
version speed of 200 ksps. See Example 19-1 for code
example.
72 74 73
V
DD
VSS
69 68 67 66 65 64 63 62 61
20
2
3
4
5
6
7
8
9
10
V
SS
VDD
13
14
15
16
50
49
V
DD
47
46
45
44
21
41
40 39 38 37 36 35 34
V
REF-
V
REF+
AV
DD
AVSS 27 28 29 30 V
SS
VDD 33
17
18
19
75
1
57
56
55
54
53
52
V
SS
60
59
58
43
42
76 78 77 79
22
80
dsPIC30F6014
VDD
VDD
VDD
VDD
VDD
VDD
VDD
R2
10
C2
0.1 μF
C1
0.01 μF
R1
10
C8
1 μF
VDD
C7
0.1 μF
VDD
C6
0.01 μF
AVDD
C5
1 μF
AVDD
C4
0.1 μF
AVDD
C3
0.01 μF
See Note 1:
Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.
1
(14 + 1) x 200,000
= 334 ns