Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 64 (14x14) 16-Bit 30 null I/O number 52

Table Of Contents

dsPIC30F6011/6012/6013/6014

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

Summary of content (228 pages)

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dsPIC30F6011/6012/6013/6014 Data Sheet High-Performance, 16-Bit Digital Signal Controllers © 2006 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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dsPIC30F6011/6012/6013/6014 dsPIC30F6011/6012/6013/6014 High-Performance Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F6011/6012/6013/6014 Special Microcontroller Features (Cont.): CMOS Technology: • Fail-Safe Clock Monitor operation: - Detects clock failure and switches to on-chip low power RC oscillator • Programmable code protection • In-Circuit Serial Programming™ (ICSP™) • Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes • • • • Low-power, high-speed Flash technology Wide operating voltage range (2.5V to 5.
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dsPIC30F6011/6012/6013/6014 Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6011 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKI VDD SC
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dsPIC30F6011/6012/6013/6014 Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6012 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2
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dsPIC30F6011/6012/6013/6014 Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC8/CN16/RD7 OC7/CN15/RD6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS RG14 CN23/RA7 CN22/RA6 RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RG13 80-Pin TQFP RG15 T2CK/RC1 1 2 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 T3CK/RC2 3 T4CK/RC3 T5CK/RC4 4 5 56 IC4/RD11 IC3/RD10 SCK2/CN8/RG6 6 55 IC2/RD9 SDI2
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dsPIC30F6011/6012/6013/6014 Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC8/CN16/RD7 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS CSCK/RG14 CN23/RA7 CN22/RA6 CSDI/RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CSDO/RG13 80-Pin TQFP 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 56 IC4/RD11 IC3/RD10 6 55 IC2/RD9 IC1/RD8 COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 T4CK/RC3 T5CK
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dsPIC30F6011/6012/6013/6014 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU Architecture Overview........................................................................................................................................................ 15 3.0 Memory Organization ................................................................
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dsPIC30F6011/6012/6013/6014 1.0 DEVICE OVERVIEW Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 FIGURE 1-1: dsPIC30F6011/6012 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 24 16 16 Data Latch Data Latch Y Data RAM X Data RAM Address Latch Address Latch 16 24 Address Latch Program Memory (Up to 144 Kbytes) 16 Data EEPROM (Up to 4 Kbytes) 16 PGD/EMUD/AN0/VREF+/CN2/RB0 PGC/EMUC/AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 AN9/RB9 AN
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dsPIC30F6011/6012/6013/6014 FIGURE 1-2: dsPIC30F6013/6014 BLOCK DIAGRAM CN22/RA6 CN23/RA7 VREF-/RA9 VREF+/RA10 INT1/RA12 INT2/RA13 INT3/RA14 INT4/RA15 Y Data Bus X Data Bus Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 24 16 16 16 Data Latch Data Latch Y Data RAM X Data RAM Address Latch Address Latch 16 24 Address Latch Program Memory (Up to 144 Kbytes) 16 Data EEPROM (Up to 4 Kbytes) 16 PORTA PGD/EMUD/AN0/CN2/RB0 PGC/EMUC/AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5
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dsPIC30F6011/6012/6013/6014 Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN15 I Analog Pin Name Description Analog input channels.
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dsPIC30F6011/6012/6013/6014 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type OSC1 I ST/CMOS OSC2 I/O — Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. PGD PGC I/O I ST ST In-Circuit Serial Programming data input/output pin. In-Circuit Serial Programming clock input pin.
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dsPIC30F6011/6012/6013/6014 2.0 CPU ARCHITECTURE OVERVIEW Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157). 2.
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dsPIC30F6011/6012/6013/6014 The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors.
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dsPIC30F6011/6012/6013/6014 FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
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dsPIC30F6011/6012/6013/6014 2.3 Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. 2. 3. 4. 5. DIVF - 16/16 signed fractional divide DIV.sd - 32/16 signed divide DIV.ud - 32/16 unsigned divide DIV.sw - 16/16 signed divide DIV.
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dsPIC30F6011/6012/6013/6014 2.4 DSP Engine The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). The dsPIC30F is a single-cycle instruction flow architecture, therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources may be used concurrently by the same instruction (e.g., ED, EDAC).
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dsPIC30F6011/6012/6013/6014 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array DS70117F-page 20 © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 2.4.1 MULTIPLIER The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits.
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dsPIC30F6011/6012/6013/6014 The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred.
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dsPIC30F6011/6012/6013/6014 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
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dsPIC30F6011/6012/6013/6014 3.0 MEMORY ORGANIZATION Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F6011/6013 Reset - GOTO Instruction Reset - Target Address FIGURE 3-2: 000000 000002 000004 PROGRAM SPACE MEMORY MAP FOR dsPIC30F6012/6014 Reset - GOTO Instruction Reset - Target Address Vector Tables Vector Tables Alternate Vector Table User Flash Program Memory (44K instructions) Reserved (Read ‘0’s) Data EEPROM (2 Kbytes) Interrupt Vector Table 00007E 000080 000084 0000FE 000100 User Memory Space User Memory Space In
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dsPIC30F6011/6012/6013/6014 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> Instruction Access User TBLRD/TBLWT User (TBLPAG<7> = 0) TBLPAG<7:0> Data EA<15:0> TBLRD/TBLWT Configuration (TBLPAG<7> = 1) TBLPAG<7:0> Data EA<15:0> Program Space Visibility User FIGURE 3-3: <0> PC<22:1> 0 0 PSVPAG<7:0> 0 Data EA<14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter 0
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dsPIC30F6011/6012/6013/6014 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS A set of table instructions are provided to move byte or word sized data to and from program space. 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.
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dsPIC30F6011/6012/6013/6014 FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 TBLRDH.B (Wn<0> = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page.
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dsPIC30F6011/6012/6013/6014 FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Program Space 0x000100 Data Space 0x0000 PSVPAG(1) 0x01 8 15 EA<15> = 0 Data 16 Space 15 EA EA<15> = 1 0x8000 15 Address Concatenation 23 23 15 0 0x008000 Upper Half of Data Space is Mapped into Program Space 0xFFFF 0x017FFF BSET MOV MOV MOV CORCON,#2 #0x01, W0 W0, PSVPAG 0x8000, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an
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dsPIC30F6011/6012/6013/6014 3.2 Data Address Space The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. 3.2.1 DATA SPACE MEMORY MAP The data space memory is split into two blocks, X and Y data space.
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dsPIC30F6011/6012/6013/6014 FIGURE 3-7: DATA SPACE MEMORY MAP FOR dsPIC30F6011/6013 MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 6 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70117F-page 32 0xFFFE © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 FIGURE 3-8: DATA SPACE MEMORY MAP FOR dsPIC30F6012/6014 MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 0x1FFF 0x1FFE Y Data RAM (Y) 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE X SPACE SFR SPACE UNUSED Y SPACE UNUSED X SPACE X SPACE (Y SPACE) UNUSED Non-MAC Class Ops (Read) MAC Class Ops (Read) Indirect EA from any W TABLE 3-2: Indirect EA from W8, W9 EFFECT OF INVALID MEMORY ACCESSES Attempted Operation Data Returned EA = an unimplemented address 0x0000 W8 or W9 used to access Y data space in a MAC instruction 0x0000 W10 or W11 used to access X data
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dsPIC30F6011/6012/6013/6014 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the instruction will be executed but the write will not occur.
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SFR Name CORE REGISTER MAP Address (Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State W0 0000 W0 / WREG 0000 0000 0000 0000 W1 0002 W1 0000 0000 0000 0000 W2 0004 W2 0000 0000 0000 0000 W3 0006 W3 0000 0000 0000 0000 W4 0008 W4 0000 0000 0000 0000 W5 000A W5 0000 0000 0000 0000 W6 000C W6 0000 0000 0000 0000 W7 000E W7 0000 0000 0000 0000 © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 4.0 ADDRESS GENERATOR UNITS Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.
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dsPIC30F6011/6012/6013/6014 4.2.1 START AND END ADDRESS 4.2.2 The Modulo Addressing scheme requires that a starting and an ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT, YMODEND (see Table 3-3). Note: Y space Modulo Addressing EA calculations assume word sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified.
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dsPIC30F6011/6012/6013/6014 4.2.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the effective address calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
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dsPIC30F6011/6012/6013/6014 FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address A3 A2 A1 A0 Bit-Reversed Address Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0
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dsPIC30F6011/6012/6013/6014 5.0 INTERRUPTS Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 5.1 Interrupt Priority The user assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user. Note: The user selectable priority levels start at 0 as the lowest priority and level 7 as the highest priority.
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dsPIC30F6011/6012/6013/6014 5.2 Reset Sequence A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location immediately followed by the address target for the GOTO instruction.
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dsPIC30F6011/6012/6013/6014 6. Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address. Executing instructions after modifying the PC to point to unimplemented program memory addresses. The PC may be modified by loading a value into the stack and executing a RETURN instruction. FIGURE 5-1: Decreasing Priority 5. Stack Error Trap: IVT This trap is initiated under the following conditions: 1. 2.
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dsPIC30F6011/6012/6013/6014 FIGURE 5-2: Stack Grows Towards Higher Address 0x0000 15 INTERRUPT STACK FRAME 0 PC<15:0> SRL IPL3 PC<22:16> W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH: [W15++] Note 1: The user can always lower the priority level by writing a new value into SR. The Interrupt Service Routine must clear the interrupt flag bits in the IFSx register before lowering the processor interrupt priority, in order to avoid recursive interrupts.
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SFR Name ADR INTERRUPT CONTROLLER REGISTER MAP Bit 15 INTCON1 0080 NSTDIS Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR Bit 2 Bit 1 STKERR OSCFAIL Bit 0 Reset State — 0000 0000 0000 0000 INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF
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dsPIC30F6011/6012/6013/6014 6.0 FLASH PROGRAM MEMORY 6.2 Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 6.4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. Each panel consists of 128 rows or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary.
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dsPIC30F6011/6012/6013/6014 6.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 6.6.1 4. 5.
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dsPIC30F6011/6012/6013/6014 6.6.3 LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer.
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dsPIC30F6011/6012/6013/6014 7.0 DATA EEPROM MEMORY Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 7.2 7.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register. Setting the WR bit initiates the erase as shown in Example 7-2.
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dsPIC30F6011/6012/6013/6014 7.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase data EEPROM word. a) Select word, data EEPROM erase, and set WREN bit in NVMCON register. b) Write address of word to be erased into NVMADR. c) Enable NVM interrupt (optional). d) Write ‘55’ to NVMKEY. e) Write ‘AA’ to NVMKEY. f) Set the WR bit. This will begin erase cycle. g) Either poll NVMIF bit or wait for NVMIF interrupt.
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dsPIC30F6011/6012/6013/6014 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block.
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dsPIC30F6011/6012/6013/6014 7.4 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in.
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dsPIC30F6011/6012/6013/6014 8.0 I/O PORTS Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
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dsPIC30F6011/6012/6013/6014 8.2 Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. FIGURE 8-2: When reading the Port register, all pins configured as analog input channels will read as cleared (a low level).
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SFR Name PORTD REGISTER MAP FOR dsPIC30F6011/6012 Addr.
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dsPIC30F6011/6012/6013/6014 8.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor, in response to a change of state on selected input pins. This module is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. There are up to 24 external signals (CN0 through CN23) that may be selected (enabled) for generating an interrupt request on a change of state.
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dsPIC30F6011/6012/6013/6014 9.0 TIMER1 MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the 16-bit General Purpose Timer1 module and associated operational modes.
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dsPIC30F6011/6012/6013/6014 FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM PR1 Equal Comparator x 16 TSYNC 1 Reset Sync TMR1 0 T1IF Event Flag 0 1 Q D Q CK TGATE TCS TGATE TGATE TON SOSCO/ T1CK 1x LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode.
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dsPIC30F6011/6012/6013/6014 9.4 9.5.1 Timer Interrupt RTC OSCILLATOR OPERATION The 16-bit timer has the ability to generate an interrupt on period match. When the timer count matches the Period register, the T1IF bit is asserted and an interrupt will be generated if enabled. The T1IF bit must be cleared in software. The timer interrupt flag, T1IF, is located in the IFS0 Control register in the interrupt controller.
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SFR Name Addr. TIMER1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TON — TSIDL — — — — — — TGATE Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Reset State uuuu uuuu uuuu uuuu 1111 1111 1111 1111 TCKPS1 TCKPS0 Legend: u = uninitialized bit Note: Bit 3 Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F6011/6012/6013/6014 10.0 TIMER2/3 MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the 32-bit General Purpose Timer module (Timer2/3) and associated operational modes.
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dsPIC30F6011/6012/6013/6014 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 MSB LSB Sync ADC Event Trigger Equal Comparator x 32 PR3 T3IF Event Flag PR2 0 1 Q D Q CK TGATE (T2CON<6>) TCS TGATE TGATE (T2CON<6>) TON T2CK Note: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 Timer Configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation.
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dsPIC30F6011/6012/6013/6014 FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Reset T2IF Event Flag Comparator x 16 TMR2 Sync 0 1 Q D Q CK TGATE TCS TGATE TGATE TON T2CK FIGURE 10-3: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal Comparator x 16 TMR3 Reset 0 1 Q D Q CK TGATE T3CK TGATE TCS TGATE T3IF Event Flag Sync TON 1x 01 TCY © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 10.1 Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).
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dsPIC30F6011/6012/6013/6014 11.0 TIMER4/5 MODULE • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral modules, such as input capture and output compare Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
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dsPIC30F6011/6012/6013/6014 FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Reset TMR4 Sync 0 1 Q D Q CK TGATE TCS TGATE T4IF Event Flag Comparator x 16 TGATE TON T4CK FIGURE 11-3: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER5 BLOCK DIAGRAM PR5 ADC Event Trigger Equal Reset TMR5 0 1 Q D Q CK TGATE TCS TGATE T5IF Event Flag Comparator x 16 TGATE T5CK TON Sync 1x 01 TCY Note: TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 In the dsPIC30F6011
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dsPIC30F6011/6012/6013/6014 12.0 INPUT CAPTURE MODULE These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain up to 8 capture channels (i.e., the maximum value of N is 8). Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
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dsPIC30F6011/6012/6013/6014 12.1.2 CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO.
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dsPIC30F6011/6012/6013/6014 13.0 OUTPUT COMPARE MODULE The key operational features of the output compare module include: Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the output compare module and associated operational modes.
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dsPIC30F6011/6012/6013/6014 13.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.
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dsPIC30F6011/6012/6013/6014 13.4.2 PWM PERIOD When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1. • TMRx is cleared. • The OCx pin is set. - Exception 1: If PWM duty cycle is 0x0000, the OCx pin will remain low. - Exception 2: If duty cycle is greater than PRx, the pin will remain high.
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SFR Name Addr.
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dsPIC30F6011/6012/6013/6014 14.0 SPI MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Serial Peripheral Interface (SPI) module is a synchronous serial interface.
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dsPIC30F6011/6012/6013/6014 FIGURE 14-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Receive Transmit SPIxSR SDIx bit 0 SDOx SSx Shift Clock Clock Control SS and FSYNC Control Edge Select Secondary Prescaler 1:1-1:8 SCKx Primary Prescaler 1, 4, 16, 64 FCY Enable Master Clock Note: x = 1 or 2.
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dsPIC30F6011/6012/6013/6014 14.3 Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven. Also, the SPI module is resynchronized, and all counters/control circuitry are reset.
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SPI1 REGISTER MAP SFR Name Addr. Bit 15 SPI1STAT 0220 SPI1CON 0222 SPI1BUF 0224 Note: Bit 13 Bit 12 SPIEN — SPISIDL — — FRMEN SPIFSD — Bit 10 — — DISSDO MODE16 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 Transmit and Receive Buffer 0000 0000 0000 0000 0000 0000 0000 0000 SPI2 REGISTER MAP Addr.
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dsPIC30F6011/6012/6013/6014 15.0 I2C MODULE 15.1.1 Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F6011/6012/6013/6014 FIGURE 15-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read SCL Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect I2CSTAT Write Control Logic Start, Restart, Stop bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70117F-page 96 Write I2CBRG FCY Read © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 15.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 LSbs of the I2CADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
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dsPIC30F6011/6012/6013/6014 15.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 15.5 Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 15.5.
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dsPIC30F6011/6012/6013/6014 15.8 Slope Control 15.12 I2C Master Operation The I2C standard requires slope control on the SDA and SCL signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate control if desired. It is necessary to disable the slew rate control for 1 MHz mode. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition.
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dsPIC30F6011/6012/6013/6014 15.12.3 BAUD RATE GENERATOR 2 In I C Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high. As per the I2C standard, FSCK may be 100 kHz or 400 kHz. However, the user can specify any baud rate up to 1 MHz.
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dsPIC30F6011/6012/6013/6014 16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE 16.1 The key features of the UART module are: Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F6011/6012/6013/6014 FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE Write UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Load RSR to Buffer Receive Shift Register (UxRSR) Control Signals FERR UxRX 8-9 PERR LPBACK From UxTX 1 16 Divider 16x Baud Clock from Baud Rate Generator UxRXIF DS
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dsPIC30F6011/6012/6013/6014 16.2 16.2.1 Enabling and Setting Up UART ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input respectively, overriding the TRIS and LATCH register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘1’ when no transmission is taking place. 16.2.2 16.3 16.3.
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dsPIC30F6011/6012/6013/6014 16.3.4 TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit: a) b) If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty word.
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dsPIC30F6011/6012/6013/6014 Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. 16.5.2 FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’, otherwise FERR will be set. The read only FERR bit is buffered along with the received data. It is cleared on any Reset. 16.5.
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dsPIC30F6011/6012/6013/6014 16.9 Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. 16.10.
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dsPIC30F6011/6012/6013/6014 17.0 CAN MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). 17.1 Overview The Controller Area Network (CAN) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices.
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dsPIC30F6011/6012/6013/6014 FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 BUFFERS Acceptance Filter RXF2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF MESSAGE TXB1 MSGREQ TXABT TXLARB TXERR MTXBUFF TXB0 A c c e p t R X B 0 Message Queue Control Transmit Byte Sequencer Acceptance Mask RXM0 Acceptance Filter RXF3 Acceptance Filter RXF0 Acceptance Filter RXF4 Acceptance Filter RXF1 Acceptance Filter RXF5 Identifi
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dsPIC30F6011/6012/6013/6014 17.3 Modes of Operation The CAN module can operate in one of several Operation modes selected by the user. These modes include: • • • • • • Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Loopback Mode Error Recognition Mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>).
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dsPIC30F6011/6012/6013/6014 17.4 17.4.1 Message Reception RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine.
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dsPIC30F6011/6012/6013/6014 • Receive Error Interrupts: A receive error interrupt will be indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt Status register, CiINTF. - Invalid Message Received: If any type of error occurred during reception of the last message, an error will be indicated by the IVRIF bit. - Receiver Overrun: The RXnOVR bit indicates that an overrun condition occurred.
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dsPIC30F6011/6012/6013/6014 17.5.6 TRANSMIT INTERRUPTS 17.6 Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
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dsPIC30F6011/6012/6013/6014 17.6.2 PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64, in addition to a fixed divide-by-2 for clock generation. The time quantum (TQ) is a fixed unit of time derived from the oscillator period, and is given by Equation 17-1. . Note: FCAN must not exceed 30 MHz. If CANCKS = 0, then FCY must not exceed 7.5 MHz. EQUATION 17-1: TIME QUANTUM FOR CLOCK GENERATION TQ = 2 (BRP<5:0> + 1)/FCAN 17.6.
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CAN1 REGISTER MAP SFR Name Addr.
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SFR Name CAN1 REGISTER MAP (CONTINUED) Addr. Bit 15 Bit 14 C1INTE 0398 — — C1EC 039A Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE Transmit Error Count Register Receive Error Count Register Legend: u = uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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SFR Name Addr.
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dsPIC30F6011/6012/6013/6014 18.0 DATA CONVERTER INTERFACE (DCI) MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). 18.
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dsPIC30F6011/6012/6013/6014 FIGURE 18-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate CSCK Generator FSD Word Size Selection bits 16-bit Data Bus Frame Length Selection bits DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO DS70117F-page 126 © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 18.3 18.3.1 DCI Module Operation MODULE ENABLE The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Clearing the DCIEN control bit has the effect of resetting the module. In particular, all counters associated with CSCK generation, frame sync, and the DCI buffer control unit are reset. 18.3.
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dsPIC30F6011/6012/6013/6014 18.3.6 SLAVE FRAME SYNC OPERATION When the DCI module is operating as a frame sync slave (COFSD = 1), data transfers are controlled by the Codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals. In the Multi-Channel mode, a new data frame transfer will begin one CSCK cycle after the COFS pin is sampled high (see Figure 18-2). The pulse on the COFS pin resets the frame sync generator logic.
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dsPIC30F6011/6012/6013/6014 18.3.7 BIT CLOCK GENERATOR EQUATION 18-2: The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock will be disabled. If the BCG<11:0> bits are set to a nonzero value, the bit clock generator is enabled.
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dsPIC30F6011/6012/6013/6014 18.3.8 SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sampled on the falling edge of the CSCK signal. If the CSCK bit is set, data will be sampled on the rising edge of CSCK.
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dsPIC30F6011/6012/6013/6014 18.3.14 BUFFER LENGTH CONTROL The amount of data that is buffered between interrupts is determined by the buffer length (BLEN<1:0>) control bits in the DCICON2 SFR. The size of the transmit and receive buffers may be varied from 1 to 4 data words using the BLEN control bits. The BLEN control bits are compared to the current value of the DCI buffer control unit address counter.
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dsPIC30F6011/6012/6013/6014 18.3.18 SLOT STATUS BITS The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers. 18.3.
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dsPIC30F6011/6012/6013/6014 The 20-bit mode treats each 256-bit AC-Link frame as sixteen, 16-bit time slots. In the 20-bit AC-Link mode, the module operates as if COFSG<3:0> = 1111 and WS<3:0> = 1111. The data alignment for 20-bit data slots is ignored. For example, an entire AC-Link data frame can be transmitted and received in a packed fashion by setting all bits in the TSCON and RSCON SFRs.
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DCI REGISTER MAP SFR Name Addr.
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dsPIC30F6011/6012/6013/6014 19.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The ADC module has six 16-bit registers: • • • • • • Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The ADCON1, ADCON2 and ADCON3 registers control the operation of the A/D module.
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dsPIC30F6011/6012/6013/6014 19.1 ADC Result Buffer 19.3 Selecting the Conversion Sequence The module contains a 16-word dual port read only buffer, called ADCBUF0...ADCBUFF, to buffer the ADC results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data formats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software.
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dsPIC30F6011/6012/6013/6014 19.4 Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to 4 alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit will cause the conversion trigger.
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dsPIC30F6011/6012/6013/6014 19.7 ADC Speeds The dsPIC30F 12-bit ADC specifications permit a maximum of 200 ksps sampling rate. The table below summarizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-bit ADC Conversion Rates Speed Up to 200 ksps(1) TAD Sampling Minimum Time Min 334 ns 1 TAD Rs Max VDD Temperature 2.5 kΩ 4.5V to 5.
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dsPIC30F6011/6012/6013/6014 The following figure depicts the recommended circuit for the conversion rates above 200 ksps. The dsPIC30F6014 is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 63 62 61 65 64 VSS 69 68 67 66 1 60 2 59 3 4 58 5 6 56 7 54 8 9 53 57 C2 0.1 μF dsPIC30F6014 C6 0.01 μF VDD 49 R1 10 AVDD C5 1 μF AVDD C4 0.1 μF AVDD C3 0.
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dsPIC30F6011/6012/6013/6014 FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 TAD SAMPLING TIME TSAMP = 1 TAD TSAMP = 1 TAD ADCLK TCONV = 14 TAD TCONV = 14 TAD SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM DS70117F-page 140 © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 19.8 A/D Acquisition Requirements The analog input model of the 12-bit A/D converter is shown inFigure 19-4. The total sampling time for the A/D is a function of the internal amplifier settling time and the holding capacitor charge time. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin.
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dsPIC30F6011/6012/6013/6014 19.9 Module Power-down Modes The module has 2 internal Power modes. When the ADON bit is ‘1’, the module is in Active mode; it is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings. In order to return to the Active mode from Off mode, the user must wait for the ADC circuitry to stabilize. 19.10 ADC Operation During CPU Sleep and Idle Modes 19.10.
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dsPIC30F6011/6012/6013/6014 19.13 Configuring Analog Port Pins 19.14 Connection Considerations The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The analog inputs have diodes to VDD and VSS as ESD protection. This requires that the analog input be between VDD and VSS.
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A/D CONVERTER REGISTER MAP SFR Name Addr.
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dsPIC30F6011/6012/6013/6014 20.0 SYSTEM INTEGRATION Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2. XT 4 MHz-10 MHz crystal on OSC1:OSC2. XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled(1). LP 32 kHz crystal on SOSCO:SOSCI(2). HS 10 MHz-25 MHz crystal. EC External clock input (0-40 MHz).
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dsPIC30F6011/6012/6013/6014 FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 OSC2 Primary Oscillator PLL x4, x8, x16 PLL Lock COSC<1:0> Primary Osc NOSC<1:0> Primary Oscillator Stability Detector POR Done OSWEN Oscillator Start-up Timer Clock Secondary Osc Switching and Control Block SOSCO SOSCI 32 kHz LP Oscillator Secondary Oscillator Stability Detector 2 POST<1:0> Internal Fast RC Oscillator (FRC) FRC Internal Low
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dsPIC30F6011/6012/6013/6014 20.2 Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) b) FOS<1:0> Configuration bits that select one of four oscillator groups, and FPR<3:0> Configuration bits that select one of 13 oscillator choices within the primary group. The selection is as shown in Table 20-2.
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dsPIC30F6011/6012/6013/6014 20.2.4 PHASE LOCKED LOOP (PLL) The PLL multiplies the clock which is generated by the primary oscillator. The PLL is selectable to have either gains of x4, x8, and x16. Input and output frequency ranges are summarized in Table 20-3. TABLE 20-3: PLL FREQUENCY RANGE FIN PLL Multiplier FOUT 4 MHz-10 MHz x4 16 MHz-40 MHz 4 MHz-10 MHz x8 32 MHz-80 MHz 4 MHz-7.
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dsPIC30F6011/6012/6013/6014 If the oscillator has a very slow start-up time coming out of POR, BOR or Sleep, it is possible that the PWRT timer will expire before the oscillator has started. In such cases, the FSCM will be activated and the FSCM will initiate a clock failure trap, and the COSC<1:0> bits are loaded with FRC oscillator selection. This will effectively shut off the original oscillator that was trying to start.
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dsPIC30F6011/6012/6013/6014 20.
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dsPIC30F6011/6012/6013/6014 FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset DS70117F-page 152 © 2006 Microchip
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dsPIC30F6011/6012/6013/6014 20.3.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer has not expired (if a crystal oscillator is used).
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dsPIC30F6011/6012/6013/6014 Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column.
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dsPIC30F6011/6012/6013/6014 Table 20-6 shows a second example of the bit conditions for the RCON register. In this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column.
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dsPIC30F6011/6012/6013/6014 20.4 20.4.1 Watchdog Timer (WDT) WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free-running timer which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the crystal oscillator) fails. 20.4.
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dsPIC30F6011/6012/6013/6014 Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The Sleep status bit in the RCON register is set upon wake-up. Note: In spite of various delays applied (TPOR, TLOCK and TPWRT), the crystal oscillator (and PLL) may not be active at the end of the time-out (e.g., for low-frequency crystals).
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dsPIC30F6011/6012/6013/6014 20.8 Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state.
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dsPIC30F6011/6012/6013/6014 21.0 INSTRUCTION SET SUMMARY Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157).
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dsPIC30F6011/6012/6013/6014 All instructions are a single word, except for certain double-word instructions, which were made doubleword instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP.
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dsPIC30F6011/6012/6013/6014 TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register ∈ {W0..
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dsPIC30F6011/6012/6013/6014 TABLE 21-2: Base Instr # 1 2 3 4 5 6 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA Assembly Syntax Description # of # of Words Cycles Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
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dsPIC30F6011/6012/6013/6014 TABLE 21-2: Base Instr # 9 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTG BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS
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dsPIC30F6011/6012/6013/6014 TABLE 21-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax Description # of # of Words Cycles Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
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dsPIC30F6011/6012/6013/6014 TABLE 21-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
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dsPIC30F6011/6012/6013/6014 TABLE 21-2: Base Instr # 66 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC Assembly Syntax Description # of # of Words Cycles Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
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dsPIC30F6011/6012/6013/6014 22.
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dsPIC30F6011/6012/6013/6014 22.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
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dsPIC30F6011/6012/6013/6014 22.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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dsPIC30F6011/6012/6013/6014 22.11 PICSTART Plus Development Programmer 22.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
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dsPIC30F6011/6012/6013/6014 23.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below.
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dsPIC30F6011/6012/6013/6014 TABLE 23-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Operating Junction Temperature Range TJ Operating Ambient Temperature Range TA Operating Junction Temperature Range Operating Ambient Temperature Range Typ Max Unit -40 +125 °C -40 +85 °C TJ -40 +150 °C TA -40 +85 °C Operating Junction Temperature Range TJ -40 +150 °C Operating Ambient Temperature Range TA -40 +125 °C dsPIC30F601x-30I dsPIC30F601x-20I dsPIC30F601x-20E Power Dissipati
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dsPIC30F6011/6012/6013/6014 TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC31a DC31b 6.8 6.3 10 10 mA mA 25°C 85°C DC31c DC31e 6.
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dsPIC30F6011/6012/6013/6014 TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IIDLE)(2) DC51a 6.3 9 mA 25°C DC51b 5.9 9 mA 85°C DC51c 5.
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dsPIC30F6011/6012/6013/6014 TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units — μA Conditions Power Down Current (IPD) DC60a 0.3 25°C DC60b 2 60 μA 85°C DC60c 23 120 μA 125°C DC60e 0.
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dsPIC30F6011/6012/6013/6014 TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.
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dsPIC30F6011/6012/6013/6014 TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Typ(1) Max Units — 0.6 V IOL = 8.5 mA, VDD = 5V Conditions Output Low Voltage(2) DO10 I/O ports — — — TBD V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKO — — 0.6 V IOL = 1.
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dsPIC30F6011/6012/6013/6014 TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param No. LV10 Characteristic(1) Min Typ Max Units LVDL Voltage on VDD transition LVDL = 0000(2) high to low — — — V LVDL = 0001(2) — — — V (2) — — — V LVDL = 0011(2) — — — V LVDL = 0100 2.50 — 2.65 V LVDL = 0101 2.70 — 2.
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dsPIC30F6011/6012/6013/6014 TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param No. BO10 Symbol VBOR Min Typ(1) Max Units BORV = 11(3) — — — V BORV = 10 2.6 — 2.71 V BORV = 01 4.1 — 4.4 V BORV = 00 4.58 — 4.
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dsPIC30F6011/6012/6013/6014 23.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in DC Spec Section 23.0 “Electrical Characteristics”.
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dsPIC30F6011/6012/6013/6014 TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic Min Typ(1) Max Units External CLKI Frequency(2) (External clocks allowed only in EC mode) DC 4 4 4 — — — — 40 10 10 7.
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dsPIC30F6011/6012/6013/6014 TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Characteristic(1) Symbol Min Typ(2) Max Units — — — — — — 10 10 7.5(3) 10 10 7.
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dsPIC30F6011/6012/6013/6014 TABLE 23-17: INTERNAL CLOCK TIMING EXAMPLES Note 1: 2: 3: Assumption: Oscillator Postscaler is divide by 1. Instruction Execution Cycle Time: TCY = 1 / MIPS. Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 [since there are 4 Q clocks per instruction cycle]. TABLE 23-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY(2) AC CHARACTERISTICS Param No. Standard Operating Conditions: 2.5V to 5.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 23-3 for load conditions. TABLE 23-20: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR SY10 Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F6011/6012/6013/6014 TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRX Note: Refer to Figure 23-3 for load conditions. TABLE 23-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 TABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 Symbol TtxH TtxL TtxP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Conditions Synchronous, no prescaler 0.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure 23-3 for load conditions. TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-12: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO HIGH-Z 70 CS50 LSb MSb CS30 CSDI MSb IN HIGH-Z CS31 LSb IN CS40 CS41 Note: Refer to Figure 23-3 for load conditions. © 2006 Microchip Technology Inc.
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dsPIC30F6011/6012/6013/6014 TABLE 23-29: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 SDO (CSDO) MSb LSb LSb CS76 CS75 MSb IN SDI (CSDI) CS65 CS66 TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 TABLE 23-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 TABLE 23-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP52 MSb SDOX BIT14 - - - - - -1 LSb SP30,SP31 SDIX MSb IN SP51 BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F6011/6012/6013/6014 TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 TABLE 23-35: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS34 IS31 IS30 IS33 SDA Stop Condition Start Condition FIGURE 23-21: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL IS30 IS26 IS31 IS33 IS25 SDA In IS45 IS40 IS40 SDA Out TABLE 23-36: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.
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dsPIC30F6011/6012/6013/6014 TABLE 23-36: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-22: CXTX Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CXRX Pin (input) CA20 TABLE 23-37: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F6011/6012/6013/6014 TABLE 23-38: 12-BIT ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD - 0.3 or 2.7 — Lesser of VDD + 0.3 or 5.5 V — AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.
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dsPIC30F6011/6012/6013/6014 TABLE 23-38: 12-BIT ADC MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions AD24A EOFF Offset Error -2 -1.5 -1.
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dsPIC30F6011/6012/6013/6014 FIGURE 23-23: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 DONE ADIF ADRES(0) 1 2 3 4 5 6 7 8 9 1 – Software sets ADCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in the “dsPIC30F Family Reference Manual” (DS70046), Section 18. 3 – Software clears ADCON. SAMP to start conversion.
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dsPIC30F6011/6012/6013/6014 TABLE 23-39: 12-BIT A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Clock Parameters AD50 TAD A/D Clock Period AD51 tRC A/D Internal RC Oscillator Period — 334 — ns VDD = 3-5.5V (Note 1) 1.2 1.5 1.
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dsPIC30F6011/6012/6013/6014 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 64-Lead TQFP (14x14x1mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 80-Lead TQFP (14x14x1mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
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dsPIC30F6011/6012/6013/6014 64-Lead Plastic Thin Quad Flatpack (PF) 14x14x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads = n1 p D1 D B 2 1 n α A c A1 φ β Units Number of Pins Pitch Dimension Limits n p NOM n1 Overall Height A Molded Package Thickness A2 .037 Standoff A1 .002 Foot Length L (F) φ .
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dsPIC30F6011/6012/6013/6014 80-Lead Plastic Thin Quad Flatpack (PF) 14x14x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads = n1 p D1 D B 2 1 n α c φ β L Units Number of Pins Pitch Dimension Limits n p Pins per Side n1 Overall Height A A A1 (F) A2 MILLIMETERS* INCHES MIN NOM MIN MAX NOM MAX 80 80 .026 0.65 20 20 .047 1.
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dsPIC30F6011/6012/6013/6014 APPENDIX A: REVISION HISTORY Revision F (November 2006) Previous versions of this data sheet contained Advance or Preliminary Information. They were distributed with incomplete characterization data. Revision F of this document reflects the following updates: • Supported I2C Slave Addresses (see Table 15-1) • ADC Conversion Clock selection to allow 200 kHz sampling rate (see Section 19.
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dsPIC30F6011A/6012A/6013A/6014A INDEX A A/D .................................................................................... 135 Aborting a Conversion .............................................. 137 ADCHS Register ....................................................... 135 ADCON1 Register..................................................... 135 ADCON2 Register..................................................... 135 ADCON3 Register.....................................................
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dsPIC30F6011A/6012A/6013A/6014A D Data Accumulators and Adder/Subtractor........................... 21 Data Space Write Saturation ...................................... 23 Overflow and Saturation ............................................. 21 Round Logic ................................................................ 22 Write Back................................................................... 22 Data Address Space ........................................................... 31 Alignment .............
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dsPIC30F6011A/6012A/6013A/6014A F Fast Context Saving............................................................ 49 Flash Program Memory ...................................................... 51 Control Registers ........................................................ 52 NVMADR ............................................................ 52 NVMADRU.......................................................... 52 NVMCON ............................................................ 52 NVMKEY.....................
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dsPIC30F6011A/6012A/6013A/6014A O OC/PWM Module Timing Characteristics.......................... 192 Operating Current (IDD)..................................................... 175 Oscillator Configurations ........................................................... 148 Fail-Safe Clock Monitor..................................... 149 Fast RC (FRC) .................................................. 149 Initial Clock Source Selection ........................... 148 Low Power RC (LPRC) .......................
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dsPIC30F6011A/6012A/6013A/6014A S Serial Peripheral Interface. See SPI. Simple Capture Event Mode ............................................... 83 Buffer Operation.......................................................... 84 Hall Sensor Mode ....................................................... 84 Prescaler..................................................................... 83 Timer2 and Timer3 Selection Mode............................ 84 Simple OC/PWM Mode Timing Requirements..................
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dsPIC30F6011A/6012A/6013A/6014A Timing Requirements Band Gap Start-up Time ........................................... 188 Brown-out Reset ....................................................... 187 CAN Module I/O ........................................................ 205 CLKO and I/O ........................................................... 186 DCI Module AC-Link Mode ................................................... 195 Multichannel, I2S Modes ................................... 194 External Clock .
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dsPIC30F6011/6012/6013/6014 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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dsPIC30F6011/6012/6013/6014 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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dsPIC30F6011/6012/6013/6014 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.