Datasheet

© 2011 Microchip Technology Inc. DS70150E-page 33
dsPIC30F6010A/6015
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000
CORCON 0044
— — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN
— — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1>
0 uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1>
1 uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1>
0 uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1>
1 uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052
— — DISICNT<13:0> 0000 0000 0000 0000
BSRAM 0750
— — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 0000 0000 0000
SSRAM 0752
— — — — — — — — — — — — — IW_SSR IR_SSR RL_SSR 0000 0000 0000 0000
TABLE 3-3: CORE REGISTER MAP
(1)
(CONTINUED)
SFR Name
Address
(Home)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.