Datasheet

dsPIC30F6010A/6015
DS70150E-page 230 © 2011 Microchip Technology Inc.
PWM Special Event Trigger ............................................. 106
Postscaler ................................................................ 106
PWM Time Base ................................................................ 99
Continuous Up/Down Counting Modes ......................99
Double Update Mode ............................................... 100
Free-Running Mode ................................................... 99
Postscaler ................................................................ 100
Prescaler .................................................................. 100
Single-Shot Mode ...................................................... 99
PWM Update Lockout ......................................................106
Q
QEI
16-bit Up/Down Position Counter Mode .....................92
Count Direction Status ....................................... 92
Error Checking ................................................... 92
Quadrature Encoder Interface (QEI) Module .....................91
Interrupts .................................................................... 94
Logic .......................................................................... 92
Operation During CPU Idle Mode ..............................93
Operation During CPU Sleep Mode ...........................93
Register Map .............................................................. 95
Timer Operation During CPU Idle Mode ....................94
Timer Operation During CPU Sleep Mode .................93
R
Reader Response ............................................................ 232
Reset ........................................................................ 152, 158
Reset Sequence ................................................................. 43
Reset Sources ........................................................... 43
Resets
Brown-out Rest (BOR), Programmable ...................160
POR with Long Crystal Start-up Time ......................160
POR, Operating without FSCM and PWRT .............160
Power-on Reset (POR) ............................................ 158
Revision History ............................................................... 223
RTSP Control Registers ..................................................... 50
NVMADR ................................................................... 50
NVMADRU ................................................................. 50
NVMCON ................................................................... 50
NVMKEY .................................................................... 50
S
Simple Capture Event Mode
Capture Buffer Operation ...........................................82
Capture Prescaler ......................................................81
Hall Sensor Mode ...................................................... 82
Timer2 and Timer3 Selection Mode ...........................82
Simple Output Compare Match Mode ................................ 86
Simple PWM Mode ............................................................86
Input Pin Fault Protection ...........................................86
Period ......................................................................... 87
Single-Pulse PWM Operation .......................................... 103
Software Controlled Clock Stretching (STREN = 1) ......... 115
Software Simulator (MPLAB SIM) .................................... 177
Software Stack Pointer, Frame Pointer ..............................16
CALL Stack Frame ..................................................... 31
SPI Module ....................................................................... 108
Framed SPI Support ................................................110
Operating Function Description ............................... 108
Operation During CPU Idle Mode ............................110
Operation During CPU Sleep Mode .........................110
SDOx Disable .......................................................... 108
Slave Select Synchronization .................................. 110
SPI1 Register Map ................................................... 111
SPI2 Register Map ................................................... 111
Word and Byte Communication ............................... 108
STATUS Register .............................................................. 16
Symbols Used in Opcode Descriptions ........................... 167
System Integration ........................................................... 152
Register Map for dsPIC30F6010A ........................... 165
Register Map for dsPIC30F6015 ............................. 165
T
Timer1 Module ................................................................... 65
Gate Operation .......................................................... 66
Interrupt ..................................................................... 66
Operation During Sleep Mode ................................... 66
Prescaler ................................................................... 66
Real-Time Clock ........................................................ 66
Interrupts ........................................................... 67
Oscillator Operation ........................................... 67
Register Map ............................................................. 68
16-bit Asynchronous Counter Mode .......................... 65
16-bit Synchronous Counter Mode ............................ 65
16-bit Timer Mode ...................................................... 65
Timer2 and Timer3 Selection Mode ................................... 86
Timer2/3 Module ................................................................ 69
ADC Event Trigger ..................................................... 74
Gate Operation .......................................................... 74
Interrupt ..................................................................... 74
Operation During Sleep Mode ................................... 74
Register Map ............................................................. 75
Timer Prescaler ......................................................... 74
32-bit Synchronous Counter Mode ............................ 69
32-bit Timer Mode ...................................................... 69
Timer4/5 Module ................................................................ 77
Register Map ............................................................. 79
Timing Diagrams
Band Gap Start-up Time .......................................... 195
CAN Bit .................................................................... 133
CAN I/O ................................................................... 213
Center-Aligned PWM ............................................... 101
Dead-Time ............................................................... 103
Edge-Aligned PWM ................................................. 101
External Clock .......................................................... 188
Input Capture (CAPx) .............................................. 199
I
2
C Bus Data (Master Mode) ................................... 209
I
2
C Bus Data (Slave Mode) ..................................... 211
I
2
C Bus Start/Stop Bits (Master Mode) .................... 209
I
2
C Bus Start/Stop Bits (Slave Mode) ...................... 211
Motor Control PWM ................................................. 201
Motor Control PWM Fault ........................................ 201
OC/PWM .................................................................. 200
Output Compare (OCx) ............................................ 199
PWM Output .............................................................. 87
QEA/QEB Input ....................................................... 202
QEI Module Index Pulse .......................................... 203
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ........................................ 194
SPI Master Mode (CKE = 0) .................................... 204
SPI Master Mode (CKE = 1) .................................... 205
SPI Slave Mode (CKE = 0) ...................................... 206
SPI Slave Mode (CKE = 1) ...................................... 207
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1 .................... 159
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2 .................... 159
Time-out Sequence on Power-up
(MCLR
Tied to VDD) ................................................. 159
TimerQ (QEI Module) External Clock ...................... 198
Timer1, 2, 3, 4, 5 External Clock ............................. 196