Datasheet
dsPIC30F6010A/6015
DS70150E-page 158 © 2011 Microchip Technology Inc.
FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 1
FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
MCLR
TPWRT
TOST
VDD
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
MCLR
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST