Datasheet

© 2011 Microchip Technology Inc. DS70150E-page 155
dsPIC30F6010A/6015
21.2.2 OSCILLATOR START-UP TIMER
(OST)
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an Oscillator
Start-up Timer is included. It is a simple 10-bit counter
that counts 1024 T
OSC cycles before releasing the
oscillator clock to the rest of the system. The time-out
period is designated as T
OST. The TOST time is involved
every time the oscillator has to restart (i.e., on POR,
BOR and wake-up from Sleep). The Oscillator Start-up
Timer is applied to the LP, XT, XTL and HS Oscillator
modes (upon wake-up from Sleep, POR and BOR) for
the primary oscillator.
21.2.3 LP OSCILLATOR CONTROL
Enabling the LP oscillator is controlled with two
elements:
• The current oscillator group bits COSC<2:0>
• The LPOSCEN bit (OSCCON register)
The LP oscillator is ON (even during Sleep mode) if
LPOSCEN = 1. The LP oscillator is the device clock if:
•
COSC<2:0> = 000 (LP selected as main oscillator)
and
• LPOSCEN = 1
Keeping the LP oscillator ON at all times allows for a
fast switch to the 32 kHz system clock for lower power
operation. Returning to the faster main oscillator will
still require a start-up time.
21.2.4 PHASE-LOCKED LOOP (PLL)
The PLL multiplies the clock which is generated by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8 and x16. Input and output frequency
ranges are summarized in Table 21-3.
TABLE 21-3: PLL FREQUENCY RANGE
The PLL features a lock output, which is asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal will be
rescinded. The state of this signal is reflected in the
read-only LOCK bit in the OSCCON register.
21.2.5 FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (7.37 MHz nominal) internal
RC oscillator. This oscillator is intended to provide rea-
sonable device operating speeds without the use of an
external crystal, ceramic resonator or RC network. The
FRC oscillator can be used with the PLL to obtain
higher clock frequencies.
The dsPIC30F operates from the FRC oscillator when-
ever the current oscillator selection control bits in the
OSCCON register (OSCCON<14:12>) are set to ‘001’.
The 6-bit field specified by TUN<5:0> (OSCTUN<5:0>)
allows the user to tune the internal fast RC oscillator
(nominal 7.37 MHz). The user can tune the FRC oscil-
lator within a range of +12.6% (930 kHz) and -13% (960
kHz) in steps of 0.4% around the factory-calibrated set-
ting, see Table 21-4.
If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are
set to ‘00101’, ‘00110’ or ‘00111’, then a PLL
multiplier of 4, 8 or 16 (respectively) is applied.
TABLE 21-4: FRC TUNING
Fin
PLL
Multiplier
Fout
4 MHz-10 MHz x4 16 MHz-40 MHz
4 MHz-10 MHz x8 32 MHz-80 MHz
4 MHz-7.5 MHz x16 64 MHz-120 MHz
Note: OSCTUN functionality has been provided
to help customers compensate for
temperature effects on the FRC frequency
over a wide range of temperatures. The
tuning step size is an approximation and is
neither characterized nor tested.
Note: When a 16x PLL is used, the FRC oscilla-
tor must not be tuned to a frequency
greater than 7.5 MHz.
TUN<5:0>
Bits
FRC Frequency
01 1111 +12.6%
01 1110 +12.2%
01 1101 +11.8%
... ...
00 0100 +1.6%
00 0011 +1.2%
00 0010 +0.8%
00 0001 +0.4%
00 0000 Center Frequency (oscillator is
running at calibrated frequency)
11 1111 -0.4%
11 1110 -0.8%
11 1101 -1.2%
11 1100 -1.6%
... ...
10 0011 -11.8%
10 0010 -12.2%
10 0001 -12.6%
10 0000 -13.0%