Datasheet

dsPIC30F6010A/6015
DS70150E-page 108 © 2011 Microchip Technology Inc.
FIGURE 16-1: SPI BLOCK DIAGRAM
FIGURE 16-2: SPI MASTER/SLAVE CONNECTION
Note: x = 1 or 2.
Read Write
Internal
Data Bus
SDIx
SDOx
SSx
SCKx
SPIxSR
SPIxBUF
bit 0
Shift
clock
Edge
Select
F
CY
Primary
1, 4, 16, 64
Enable Master Clock
Prescaler
Secondary
Prescaler
1:1-1:8
SS & FSYNC
Control
Clock
Control
Transmit
SPIxBUF
Receive
Serial Input Buffer
(SPIxBUF)
Shift Register
(SPIxSR)
MSb
LSb
SDOx
SDIx
PROCESSOR 1
SCKx
SPI Master
Serial Input Buffer
(SPIyBUF)
Shift Register
(SPIySR)
LSb
MSb
SDIy
SDOy
PROCESSOR 2
SCKy
SPI Slave
Serial Clock
Note: x = 1 or 2, y = 1 or 2.