dsPIC30F6010A/6015 Data Sheet High-Performance, 16-bit Digital Signal Controllers © 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
dsPIC30F6010A/6015 High-Performance, 16-bit Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 Special Microcontroller Features: CMOS Technology: • Enhanced Flash program memory: - 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical) • Data EEPROM memory: - 100,000 erase/write cycle (min.
dsPIC30F6010A/6015 Pin Diagram PWM3H/RE5 PWM4L/RE6 IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 67 66 65 64 63 62 61 70 69 68 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/UPDN/CN16/RD7 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 PWM2H/RE3 80 79 78 77 76 75 74 73 72 71 PWM3L/RE4 80-Pin TQFP 1 2 PWM4H/RE7 3 T2CK/RC1 T4CK/RC3 SCK2/CN8/RG6 4 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 5 56 IC4/RD11 IC3/RD10 6 55 IC2/R
dsPIC30F6010A/6015 Pin Diagram 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VSS OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F6015 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/CLKO
dsPIC30F6010A/6015 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU Architecture Overview........................................................................................................................................................ 15 3.0 Memory Organization .........................................................................
dsPIC30F6010A/6015 NOTES: DS70150E-page 8 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 1.0 Note: DEVICE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 FIGURE 1-1: dsPIC30F6010A BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 16 Data Latch Y Data RAM (4 Kbytes) Address Latch 16 24 Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Address Latch Program Memory (144 Kbytes) Data EEPROM (4 Kbytes) Data Latch X Data RAM (4 Kbytes) Address Latch 16 VREF-/RA9 VREF+/RA10 INT3/RA14 INT4/RA15 PORTA PGD/EMUD/AN0/CN2/RB0 PGC/EMUC/AN1/CN3/RB1 AN2/SS1/CN4/RB
dsPIC30F6010A/6015 FIGURE 1-2: dsPIC30F6015 BLOCK DIAGRAM Y Data Bus X Data Bus Interrupt Controller PSV & Table Data Access 24 Control Block 8 16 16 16 Data Latch Y Data RAM (4 Kbytes) Address Latch 16 24 Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Address Latch Program Memory (144 Kbytes) Data EEPROM (4 Kbytes) 16 Data Latch X Data RAM (4 Kbytes) Address Latch AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/C
dsPIC30F6010A/6015 Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS Pin Type Buffer Type AN0-AN15 I Analog Analog input channels.
dsPIC30F6010A/6015 TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED) Pin Type Buffer Type FLTA FLTB PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H I I O O O O O O O O ST ST — — — — — — — — PWM Fault A input. PWM Fault B input. PWM1 Low output. PWM1 High output. PWM2 Low output. PWM2 High output. PWM3 Low output. PWM3 High output. PWM4 Low output. PWM4 High output. MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-low Reset to the device.
dsPIC30F6010A/6015 TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED) Pin Type Buffer Type U1RX U1TX U1ARX U1ATX U2RX U2TX I O I O I O ST — ST — ST — UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit. VDD P — Positive supply for logic and I/O pins. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog Voltage Reference (High) input. VREF- I Analog Analog Voltage Reference (Low) input.
dsPIC30F6010A/6015 2.0 Note: CPU ARCHITECTURE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 2.2 Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC). The working registers can act as data, address or offset registers. All registers are memory mapped.
dsPIC30F6010A/6015 FIGURE 2-1: dsPIC30F6010A/6015 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC30F6010A/6015 2.3 Divide Support 2.4 The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: • • • • • DIVF – 16/16 signed fractional divide DIV.sd – 32/16 signed divide DIV.ud – 32/16 unsigned divide DIV.s – 16/16 signed divide DIV.
dsPIC30F6010A/6015 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 Barrel Shifter 16 X Data Bus 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 2.4.1 MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operations and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17x17-bit multiplier/ scaler is a 33-bit value, which is sign-extended to 40 bits.
dsPIC30F6010A/6015 The SA and SB bits are modified each time data passes through the adder/subtractor, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated if saturation is enabled. When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred.
dsPIC30F6010A/6015 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtractor saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.
dsPIC30F6010A/6015 Note: 3.1 MEMORY ORGANIZATION FIGURE 3-1: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Instruction Access TBLRD/TBLWT TBLRD/TBLWT Program Space Visibility FIGURE 3-2: User User (TBLPAG<7> = 0) Configuration (TBLPAG<7> = 1) User Program Space Address <23> <22:16> <15> <14:1> 0 PC<22:1> TBLPAG<7:0> Data EA <15:0> TBLPAG<7:0> 0 <0> 0 Data EA <15:0> PSVPAG<7:0> Data EA <14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter 0 Select Using Program Sp
dsPIC30F6010A/6015 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS A set of table instructions are provided to move byte or word-sized data to and from program space. 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.
dsPIC30F6010A/6015 FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 TBLRDH.B (Wn<0> = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page.
dsPIC30F6010A/6015 FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x000100 0x0000 PSVPAG(1) 0x00 8 15 EA<15> = 0 Data Space EA 16 15 EA<15> = 1 0x8000 Address 15 Concatenation 23 23 15 0 0x001200 Upper half of Data Space is mapped into Program Space 0x017FFE 0xFFFF BSET MOV MOV MOV CORCON,#2 #0x00, W0 W0, PSVPAG 0x9200, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-bit
dsPIC30F6010A/6015 FIGURE 3-6: dsPIC30F6010A/6015 DATA SPACE MEMORY MAP Most Significant Byte Address MSB 2 Kbyte SFR Space 0x0001 Least Significant Byte Address 16 bits LSB 0x0000 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 0x1FFF 0x1FFE Y Data RAM (Y) 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70150E-page 28 0xFFFE © 2011 Microchip T
dsPIC30F6010A/6015 DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE X SPACE FIGURE 3-7: Y SPACE UNUSED X SPACE (Y SPACE) X SPACE UNUSED UNUSED Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) MAC Class Ops Read-Only Indirect EA using any W Indirect EA using W10, W11 Indirect EA using W8, W9 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 3.2.2 DATA SPACES 3.2.3 The X data space is used by all instructions and supports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions.
dsPIC30F6010A/6015 A sign-extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including the DSP instructions, operate only on words. 3.2.
SFR Name CORE REGISTER MAP(1) Address (Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State © 2011 Microchip Technology Inc.
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 NOTES: DS70150E-page 34 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 4.0 Note: ADDRESS GENERATOR UNITS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP Accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, Move and Accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.
dsPIC30F6010A/6015 4.2.1 START AND END ADDRESS 4.2.2 The Modulo Addressing scheme requires that a starting and an ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-3). Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses.
dsPIC30F6010A/6015 4.2.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
dsPIC30F6010A/6015 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1
dsPIC30F6010A/6015 NOTES: DS70150E-page 40 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 5.0 Note: INTERRUPTS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 5.1 Interrupt Priority The user-assignable Interrupt Priority bits (IP<2:0>) for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user. Note: The user-assignable priority levels start at 0, as the lowest priority and level 7, as the highest priority.
dsPIC30F6010A/6015 5.2 Reset Sequence A Reset is not a true exception because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location, immediately followed by the address target for the GOTO instruction.
dsPIC30F6010A/6015 Address Error Trap: 5.3.2 This trap is initiated when any of the following circumstances occurs: It is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the fixed priority shown in Figure 5-2 is implemented, which may require the user to check if other traps are pending in order to completely correct the Fault. 1. 2. 3. 4. A misaligned data word access is attempted.
dsPIC30F6010A/6015 5.4 Interrupt Sequence 5.5 All interrupt event flags are sampled in the beginning of each instruction cycle by the IFSx registers. A pending Interrupt Request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the Interrupt Enable register (IECx) is set. For the remainder of the instruction cycle, the priorities of all pending interrupt requests are evaluated.
SFR Name ADR INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6010A(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP Bit 3 Bit 2 Bit 1 ADDRERR STKERR OSCFAIL INT3EP INT2EP INT1EP Bit 0 Reset State — 0000 0000 0000 0000 INT0EP 0000 0000 0000 0000 IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 NOTES: DS70150E-page 48 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 6.0 FLASH PROGRAM MEMORY Note: 6.2 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 6.4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program 32 instructions at one time. Each panel of program memory contains write latches that hold 32 instructions of programming data.
dsPIC30F6010A/6015 6.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 6.6.1 4. 5.
dsPIC30F6010A/6015 6.6.3 LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer.
© 2011 Microchip Technology Inc. NVM REGISTER MAP(1) TABLE 6-1: Addr. Bit 15 Bit 14 Bit 13 NVMCON File Name 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 NVMKEY Legend: Note 1: Bit 12 Bit 11 Bit 10 — — — Bit 9 — Bit 8 Bit 7 TWRI — Bit 6 Bit 5 Bit 4 Bit 3 NVMADR<15:0> — — — — — — — — 0766 — — — — — — — — u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6010A/6015 NOTES: DS70150E-page 54 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 7.0 Note: DATA EEPROM MEMORY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 7.2 7.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. Setting the WR bit initiates the erase, as shown in Example 7-2.
dsPIC30F6010A/6015 7.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase data EEPROM word. a) Select word, data EEPROM, erase and set WREN bit in NVMCON register. b) Write address of word to be erased into NVMADRU/NVMADR. c) Enable NVM interrupt (optional). d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit. This will begin erase cycle. g) Either poll NVMIF bit or wait for NVMIF interrupt.
dsPIC30F6010A/6015 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: 7.
dsPIC30F6010A/6015 8.0 Note: I/O PORTS Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6010A/6015 FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Output Multiplexers Peripheral Module Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Peripheral Output Data 0 PIO Module 1 Output Enable Output Data 0 Read TRIS I/O Pad Data Bus D WR TRIS Q CK TRIS Latch D WR LAT + WR Port Q CK Data Latch Read LAT Input Data Read Port 8.
© 2011 Microchip Technology Inc. TABLE 8-1: SFR Name Addr.
SFR Name dsPIC30F6015 PORT REGISTER MAP(1) Addr.
dsPIC30F6010A/6015 8.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change-ofstate on selected input pins. This module is capable of detecting input change-of-states, even in Sleep mode when the clocks are disabled.
dsPIC30F6010A/6015 NOTES: DS70150E-page 64 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 9.0 Note: TIMER1 MODULE These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 91 presents a block diagram of the 16-bit timer module. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6010A/6015 9.1 Timer Gate Operation 9.4 Timer Interrupt The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0). The 16-bit timer has the ability to generate an interrupt on period match.
dsPIC30F6010A/6015 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal, up to the value specified in the period register, and is then reset to ‘0’. The TSYNC bit must be asserted to a logic ‘0’ (Asynchronous mode) for correct operation. Enabling LPOSCEN (OSCCON<1>) will disable the normal Timer and Counter modes and enable a timer carry-out wake-up event.
SFR Name Addr. TIMER1 REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 Legend: Note 1: TON — TSIDL — — — — — — TGATE u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6010A/6015 10.0 Note: TIMER2/3 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the 32-bit General Purpose (GP) Timer module (Timer2/3) and associated operational modes.
dsPIC30F6010A/6015 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM FOR dsPIC30F6010A Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 MSB LSB Sync ADC Event Trigger Equal Comparator x 32 PR3 PR2 0 T3IF Event Flag 1 D Q CK TGATE (T2CON<6>) TCS TGATE TGATE (T2CON<6>) Q TON T2CK Note: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation.
dsPIC30F6010A/6015 FIGURE 10-2: 32-BIT TIMER2/3 BLOCK DIAGRAM FOR dsPIC30F6015 Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 MSB LSB Sync ADC Event Trigger Equal Comparator x 32 PR3 PR2 0 T3IF Event Flag 1 D Q CK TGATE(T2CON<6>) TCS TGATE TGATE (T2CON<6>) Q TON TCKPS<1:0> 2 1x Note: Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation.
dsPIC30F6010A/6015 FIGURE 10-3: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) FOR dsPIC30F6010A PR2 Equal Reset TMR2 Sync 0 1 Q D Q CK TGATE TCS TGATE T2IF Event Flag Comparator x 16 TGATE TON T2CK FIGURE 10-4: TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) FOR DSPIC30F6015 PR2 Equal Reset TMR2 Sync 0 1 Q D Q CK TGATE TCS TGATE T2IF Event Flag Comparator x 16 TGATE TON TCKPS<1:0> 2 1x Gate Sync 01 TCY 00 Prescaler
dsPIC30F6010A/6015 FIGURE 10-5: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER) PR3 ADC Event Trigger Equal Reset TMR3 0 1 Q D Q CK TGATE TCS TGATE T3IF Event Flag Comparator x 16 TGATE Sync TON 1x 01 TCY TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 Note: The dsPIC30F6010A/6015 devices do not have an external pin input to Timer3. These modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 10.1 Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).
© 2011 Microchip Technology Inc. TABLE 10-1: SFR Name Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 76 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 11.0 TIMER4/5 MODULE Note: The Timer4/5 module is similar in operation to the Timer2/3 module. However, there are some differences, which are listed below: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6010A/6015 FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM (TYPE B TIMER) PR4 Equal Comparator x 16 TMR4 Reset Sync 0 1 Q D Q CK TGATE TCS TGATE TGATE T4IF Event Flag TCKPS<1:0> 2 TON T4CK 1x FIGURE 11-3: Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 16-BIT TIMER5 BLOCK DIAGRAM (TYPE C TIMER) PR5 Equal ADC Event Trigger Comparator x 16 TMR5 Reset 0 1 Q D Q CK TGATE TCS TGATE TGATE T5IF Event Flag TCKPS<1:0> TON Sync 01 TCY 2 1x Prescaler 1, 8, 64, 256 00 Note: T
© 2011 Microchip Technology Inc. TABLE 11-1: SFR Name Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 80 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 12.0 INPUT CAPTURE MODULE Note: 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6010A/6015 12.1.2 CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer, which is four 16-bit words deep. There are two status flags, which provide status on the FIFO buffer: • ICBNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO. As each word is read from the FIFO, the remaining words are advanced by one position within the buffer.
© 2011 Microchip Technology Inc. TABLE 12-1: SFR Name Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 84 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 13.0 OUTPUT COMPARE MODULE Note: The key operational features of the output compare module include: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). • • • • • • This section describes the output compare module and associated operational modes.
dsPIC30F6010A/6015 13.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers; Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 13.
dsPIC30F6010A/6015 13.4.2 PWM PERIOD The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1. EQUATION 13-1: PWM PERIOD PWM Period = [(PRx) + 1] • 4 • TOSC • (TMRx Prescale Value) PWM frequency is defined as 1/[PWM period]. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. • The OCx pin is set.
dsPIC30F6010A/6015 13.5 Output Compare Operation During CPU Sleep Mode When the CPU enters the Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state. For example, if the pin was high when the CPU entered the Sleep state, the pin will remain high. Likewise, if the pin was low when the CPU entered the Sleep state, the pin will remain low.
© 2011 Microchip Technology Inc. TABLE 13-1: OUTPUT COMPARE REGISTER MAP(1) SFR Name Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 90 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 14.
dsPIC30F6010A/6015 14.1 Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship. If Phase A leads Phase B, then the direction (of the motor) is deemed positive or forward.
dsPIC30F6010A/6015 14.4 Programmable Digital Noise Filters The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. Schmitt Trigger inputs and a three-clock cycle delay filter combine to reject low level noise and large, short duration noise spikes that typically occur in noise prone applications, such as a motor system.
dsPIC30F6010A/6015 14.7.2 TIMER OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if the QEISIDL bit (QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to ‘1’. If the QEISIDL bit is cleared, the timer will function normally, as if the CPU Idle mode had not been entered. 14.
© 2011 Microchip Technology Inc. TABLE 14-1: SFR Name Addr. QEI REGISTER MAP(1) Bit 15 QEICON 0122 CNTERR — Bit 14 Bit 13 Bit 12 Bit 11 — QEISIDL INDX UPDN — — — — Bit 10 Bit 9 Bit 8 QEIM<2:0> IMV<1:0> Bit 7 Bit 6 Bit 5 SWPAB PCDOUT TQGATE CEID QEOUT DFLTCON 0124 POSCNT 0126 MAXCNT Legend: Note 1: 0128 Maximun Count<15:0> — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6010A/6015 NOTES: DS70150E-page 96 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 15.0 Note: MOTOR CONTROL PWM MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This module simplifies the task of generating multiple, synchronized Pulse-Width Modulated outputs.
dsPIC30F6010A/6015 FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFRs DTCON2 FLTACON Fault Pin Control SFRs FLTBCON OVDCON PWM Manual Control SFR PWM Generator 4 16-bit Data Bus PDC4 Buffer PDC4 Comparator PWM Generator 3 PTMR Channel 3 Dead-Time Generator and Override Logic Comparator PWM Generator 2 PTPER PWM Generator 1 PTPER Buffer PWM4H Channel 4 Dead-Time Generator and Override Logic PWM4L PWM3H Output Driver PWM3L Block Ch
dsPIC30F6010A/6015 15.1 PWM Time Base The PWM time base is provided by a 15-bit timer with a prescaler and postscaler. The time base is accessible via the PTMR SFR. PTMR<15> is a read-only Status bit, PTDIR, that indicates the present count direction of the PWM time base. If PTDIR is cleared, PTMR is counting upwards. If PTDIR is set, PTMR is counting downwards. The PWM time base is configured via the PTCON SFR. The time base is enabled/disabled by setting/clearing the PTEN bit in the PTCON SFR.
dsPIC30F6010A/6015 15.1.4 DOUBLE UPDATE MODE EQUATION 15-1: In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional functions to the user. First, the control loop bandwidth is doubled because the PWM duty cycles can be updated, twice per period.
dsPIC30F6010A/6015 15.4 Center-Aligned PWM 15.5.1 Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/ Down Counting mode (see Figure 15-3). The PWM compare output is driven to the active state when the value of the Duty Cycle register matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1).
dsPIC30F6010A/6015 15.6 Complementary PWM Operation In the Complementary mode of operation, each pair of PWM outputs is obtained by a complementary PWM signal. A dead time may be optionally inserted during device switching, when both outputs are inactive for a short period (Refer to Section 15.7 “Dead-Time Generators”).
dsPIC30F6010A/6015 FIGURE 15-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Time selected by DTSxA bit (A or B) 15.8 Independent PWM Output An independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PMOD bit in the PWMCON1 register is set.
dsPIC30F6010A/6015 15.11 PWM Output and Polarity Control 15.12.2 There are three device Configuration bits associated with the PWM module that provide PWM output pin control: The FLTACON and FLTBCON Special Function Registers have eight bits each that determine the state of each PWM I/O pin when it is overridden by a Fault input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. If the bit is set, the PWM I/ O pin will be driven to the active state.
dsPIC30F6010A/6015 15.13 PWM Update Lockout 15.14.1 For a complex PWM application, the user may need to write up to four Duty Cycle registers and the Time Base Period register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio.
8-OUTPUT PWM REGISTER MAP(1) SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 PTCON 01C0 PTEN — PTSIDL — — — — — PTMR 01C2 PTDIR PWM Timer Count Value 0000 0000 0000 0000 PTPER 01C4 — PWM Time Base Period Register 0111 1111 1111 1111 SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 Bit 7 Bit 6 Bit 5 Bit 4 PTOPS<3:0> Bit 3 Bit 2 PTCKPS<1:0> Bit 1 Bit 0 PTMOD<1:0> PWM Special Event Compare Register — — — — — — — PWMCON2 01CA — DTCON1 01CC DTBPS<1:0> D
dsPIC30F6010A/6015 16.0 Note: SPI MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Serial Peripheral Interface (SPI) module is a synchronous serial interface.
dsPIC30F6010A/6015 FIGURE 16-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Transmit Receive SPIxSR SDIx bit 0 SDOx Shift clock Clock Control SS & FSYNC Control SSx Edge Select Secondary Prescaler 1:1-1:8 SCKx Primary Prescaler 1, 4, 16, 64 FCY Enable Master Clock Note: x = 1 or 2.
dsPIC30F6010A/6015 16.2 Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit, FRMEN, enables framed SPI support and causes the SSx pin to perform the Frame Synchronization pulse (FSYNC) function. The control bit SPIFSD determines whether the SSx pin is an input or an output (i.e., whether the module receives or generates the Frame Synchronization pulse). The frame pulse is an active-high pulse for a single SPI clock cycle.
SPI1 REGISTER MAP(1) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 — — Bit 9 Bit 8 Bit 7 Bit 6 SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — SPI1BUF Legend: Note 1: 0224 Transmit and Receive Buffer — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6010A/6015 17.0 Note: I2C™ MODULE 17.1.1 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6010A/6015 FIGURE 17-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read SCL Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect I2CSTAT Write Control Logic Start, Restart, Stop bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70150E-page 112 Write I2CBRG FCY Read © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 17.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 Least Significant bits of the I2CADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
dsPIC30F6010A/6015 17.4.1 10-BIT MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 17.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 17.
dsPIC30F6010A/6015 17.7 Interrupts The I2C module generates two interrupt flags, MI2CIF (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Interrupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. 17.8 Slope Control The I2C standard requires slope control on the SDA and SCL signals for Fast Mode (400 kHz).
dsPIC30F6010A/6015 As per the I2C standard, FSCL may be 100 kHz or 400 kHz. However, the user can specify any baud rate up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. The Master will continue to monitor the SDA and SCL pins, and if a Stop condition occurs, the MI2CIF bit will be set. EQUATION 17-1: A write to the I2CTRN will start the transmission of data at the first data bit, regardless of where the transmitter left off when bus collision occurred.
© 2011 Microchip Technology Inc. TABLE 17-2: SFR Name Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 118 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE Note: 18.1 The key features of the UART module are: • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
dsPIC30F6010A/6015 FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE URX8 Write UxSTA UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters LPBACK 8-9 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Control Signals FERR Load RSR to Buffer Receive Shift Register (UxRSR) 1 PERR From UxTX 16 Divider 16X Baud Clock from Baud Rate Generator UxRXIF DS7015
dsPIC30F6010A/6015 18.2 18.2.1 Enabling and Setting Up UART ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input respectively, overriding the TRIS and LAT register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘1’ when no transmission is taking place. 18.2.2 18.3 18.3.1 1. 2. 3.
dsPIC30F6010A/6015 18.3.4 TRANSMIT INTERRUPT The Transmit Interrupt Flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit: a) b) If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift Register (UxTSR). This means that the transmit buffer has at least one empty word.
dsPIC30F6010A/6015 18.5.2 FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’, otherwise FERR will be set. The read-only FERR bit is buffered along with the received data. It is cleared on any Reset. 18.5.3 PARITY ERROR (PERR) The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected.
dsPIC30F6010A/6015 18.9 Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input. To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. 18.10.2 UART OPERATION DURING CPU IDLE MODE For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle.
© 2011 Microchip Technology Inc. TABLE 18-1: UART1 REGISTER MAP(1) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 8 Bit 7 020C UARTEN — USIDL — 020E UTXISEL — — — U1TXREG 0210 — — — — — U1RXREG 0212 — — — — — U1BRG Legend: Note 1: 0214 Baud Rate Generator Prescaler u = uninitialized bit; — = unimplemented bit, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 126 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 19.0 Note: 19.1 CAN MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). Overview The CAN bus module consists of a protocol engine, and message buffering/control.
dsPIC30F6010A/6015 FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 BUFFERS Acceptance Filter RXF2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB1 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB0 A c c e p t Acceptance Mask RXM0 Acceptance Filter RXF3 Acceptance Filter RXF0 Acceptance Filter RXF4 Acceptance Filter RXF1 Acceptance Filter RXF5 R X B 0 Message Queue Control Identifier M A B Data Field Transmit Byt
dsPIC30F6010A/6015 19.3 Modes of Operation The CAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization mode Disable mode Normal Operation mode Listen-Only mode Loopback mode Error Recognition mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL<10:8>). Entry into a mode is acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>).
dsPIC30F6010A/6015 19.4 19.4.1 Message Reception RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine.
dsPIC30F6010A/6015 • Receive Error Interrupts A receive error interrupt will be indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt STATUS register, CiINTF. • Invalid message received If any type of error occurred during reception of the last message, an error will be indicated by the IVRIF bit. • Receiver overrun The RXnOVR bit indicates that an overrun condition occurred.
dsPIC30F6010A/6015 19.5.6 19.6 TRANSMIT INTERRUPTS Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: • Transmit Interrupt • • • • • • At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
dsPIC30F6010A/6015 19.6.2 PRESCALER SETTING There is a programmable prescaler, with integral values ranging from 1 to 64, in addition to a fixed divideby-2 for clock generation. The Time Quantum (TQ) is a fixed unit of time derived from the oscillator period, and is given by Equation 19-1, where FCAN is FCY (if the CANCKS bit is set or 4 FCY (if CANCKS is cleared). Note: FCAN must not exceed 30 MHz. If CANCKS = 0, then FCY must not exceed 7.5 MHz.
SFR Name CAN1 REGISTER MAP FOR dsPIC30F6010A AND 6015 DEVICES(1) Addr.
© 2011 Microchip Technology Inc. TABLE 19-1: SFR Name C1TX1B2 Addr.
SFR Name CAN2 REGISTER MAP FOR dsPIC30F6010A(1) Addr.
© 2011 Microchip Technology Inc. TABLE 19-2: SFR Name C2TX1B1 Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 138 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 20.0 Note: 10-BIT HIGH-SPEED ANALOGTO-DIGITAL CONVERTER (ADC) MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The 10-bit High-Speed Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit digital number.
dsPIC30F6010A/6015 FIGURE 20-1: 10-BIT HIGH-SPEED A/D FUNCTIONAL BLOCK DIAGRAM AVDD VREF+(1) AVSS VREF-(2) AN2 + AN6 AN9 - AN1 AN4 + AN7 AN10 - AN2 AN5 + AN8 AN11 - S/H CH1 ADC 10-bit Result S/H CH2 16-word, 10-bit Dual Port Buffer S/H CH3 CH1,CH2, CH3,CH0 sample AN3 AN0 AN1 AN2 AN3 AN4 AN4 AN5 AN5 AN6 AN6 AN7 AN7 AN8 AN8 AN9 AN9 AN10 AN10 AN11 AN11 AN12 AN12 AN13 AN13 AN14 AN14 AN15 AN15 + AN1 - Note input switches S/H Sample/Sequence Control Input MU
dsPIC30F6010A/6015 20.1 A/D Result Buffer The module contains a 16-word dual port, read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 10-bits wide, but is read into different format 16-bit words. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software. 20.2 Conversion Operation After the A/D module has been configured, the sample acquisition is started by setting the SAMP bit.
dsPIC30F6010A/6015 20.4 Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to five alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit will cause the conversion trigger.
dsPIC30F6010A/6015 20.7 A/D Conversion Speeds The dsPIC30F 10-bit A/D converter specifications permit a maximum 1 Msps sampling rate. Table 20-1 summarizes the conversion speeds for the dsPIC30F 10-bit A/D converter and the required operating conditions. TABLE 20-1: 10-BIT A/D CONVERSION RATE PARAMETERS dsPIC30F 10-bit A/D Converter Conversion Rates A/D Speed Up to 1 Msps(1) TAD Sampling RS Max Minimum Time Min 83.33 ns 12 TAD 500Ω VDD Temperature 4.5V to 5.
dsPIC30F6010A/6015 The configuration guidelines give the required setup values for the conversion speeds above 500 ksps, since they require external VREF pins usage and there are some differences in the configuration procedure. Configuration details that are not critical to the conversion speed have been omitted. Figure 20-2 depicts the recommended circuit for the conversion rates above 500 ksps.
dsPIC30F6010A/6015 20.7.1.3 1 Msps Configuration Items The following configuration items are required to achieve a 1 Msps conversion rate.
dsPIC30F6010A/6015 20.8 A/D Acquisition Requirements The analog input model of the 10-bit A/D converter is shown in Figure 20-3. The total sampling time for the A/D is a function of the internal amplifier settling time, device VDD and the holding capacitor charge time. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin.
dsPIC30F6010A/6015 20.9 Module Power-Down Modes If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. The module has 3 internal power modes. When the ADON bit is ‘1’, the module is in Active mode; it is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings.
dsPIC30F6010A/6015 20.13 Configuring Analog Port Pins 20.14 Connection Considerations The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The analog inputs have diodes to VDD and VSS as ESD protection. This requires that the analog input be between VDD and VSS.
© 2011 Microchip Technology Inc. TABLE 20-2: SFR Name Addr.
dsPIC30F6010A/6015 NOTES: DS70150E-page 150 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 21.0 Note: SYSTEM INTEGRATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 TABLE 21-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1) LP 32 kHz crystal on SOSCO:SOSCI(2) HS 10 MHz-25 MHz crystal.
dsPIC30F6010A/6015 FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 OSC2 Primary Oscillator PLL x4, x8, x16 PLL Lock COSC<2:0> Primary Osc TUN<5:0> 6 NOSC<2:0> Primary Oscillator Stability Detector OSWEN Internal Fast RC Oscillator (FRC) POR Done Oscillator Start-up Timer Clock Secondary Osc Switching and Control Block SOSCO SOSCI 32 kHz LP Oscillator Secondary Oscillator Stability Detector Internal LowPower RC Oscill
dsPIC30F6010A/6015 21.2 Oscillator Configurations 21.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) b) FOS<2:0> Configuration bits that select one of four oscillator groups, and FPR<4:0> Configuration bits that select one of 16 oscillator choices within the primary group. The selection is as shown in Table 21-2. TABLE 21-2: .
dsPIC30F6010A/6015 21.2.2 OSCILLATOR START-UP TIMER (OST) In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer is included. It is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out period is designated as TOST. The TOST time is involved every time the oscillator has to restart (i.e., on POR, BOR and wake-up from Sleep).
dsPIC30F6010A/6015 21.2.6 LOW-POWER RC OSCILLATOR (LPRC) The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT and clock monitor circuits. It may also be used to provide a low frequency clock source option for applications where power consumption is critical, and timing accuracy is not required.
dsPIC30F6010A/6015 21.2.8 PROTECTION AGAINST ACCIDENTAL WRITES TO OSCCON A write to the OSCCON register is intentionally made difficult because it controls clock switching and clock scaling. To write to the OSCCON low byte, the following code sequence must be executed without any other instructions in between: Byte Write 0x46 to OSCCON low Byte Write 0x57 to OSCCON low Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction.
dsPIC30F6010A/6015 FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 21-4: VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset DS70150E-page 158 © 2011 Microchip Technology
dsPIC30F6010A/6015 21.3.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer has NOT expired (if a crystal oscillator is used).
dsPIC30F6010A/6015 Table 21-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table means that all the bits are negated prior to the action specified in the condition column.
dsPIC30F6010A/6015 21.4 21.4.1 Watchdog Timer (WDT) WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer, which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the crystal oscillator) fails. 21.4.
dsPIC30F6010A/6015 21.5.2 IDLE MODE In Idle mode, the clock to the CPU is shutdown while peripherals keep running. Unlike Sleep mode, the clock source remains active. Several peripherals have a control bit in each module, that allows them to operate during Idle. LPRC fail-safe clock remains active if clock failure detect is enabled. The processor wakes up from Idle if at least one of the following conditions is true: 21.
dsPIC30F6010A/6015 21.7 Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and STATUS registers associated with the peripheral will also be disabled so writes to those registers will have no effect and read values will be invalid.
SFR Name Addr.
dsPIC30F6010A/6015 22.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
dsPIC30F6010A/6015 Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP.
dsPIC30F6010A/6015 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register ∈ {W0..
dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Mnemonic # 1 2 3 4 5 6 7 8 ADD ADDC AND ASR BCLR BRA BSET BSW Assembly Syntax ADD ADD Acc f Description Add Accumulators f = f + WREG # of words # of cycles Status Flags Affected 1 1 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # 11 12 13 BTSS BTST BTSTS Assembly Syntax Description # of words # of cycles BTSS f,#bit4 Bit Test f, Skip if Set 1 BTST f,#bit4 Bit Test f 1 1 (2 or 3) 1 (2 or 3) 1 BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 BTST.C Ws,#bit4 Bit Test Ws to C 1 1 Status Flags Affected None None Z C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # Assembly Syntax Description # of words # of cycles 1 1 1 1 Status Flags Affected 35 36 FBCL FF1L FBCL FF1L Ws,Wnd Ws,Wnd Find Bit Change from Left (MSb) Side Find First One from Left (MSb) Side 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f=f+1 1 1 C,DC,N,OV,Z INC
dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # 52 NEG # of words # of cycles Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z Assembly Syntax NEG Acc Description Status Flags Affected NEG f f=f+1 1 1 NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z Ws,Wd Wd = Ws + 1 No Operation 1 1 1 1 C,DC,N,OV,Z None None 53 NOP NEG NOP No Operation 1 1 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-o
dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Mnemonic # 72 73 74 75 SUB SUBB SUBR SUBBR Assembly Syntax Description # of cycles 1 1 Status Flags Affected SUB f f = f – WREG 1 1 OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z C,DC,N,OV,Z SUB Acc Subtract Accumulators # of words SUB Wb,#lit5,Wd Wd = Wb – lit
dsPIC30F6010A/6015 23.
dsPIC30F6010A/6015 23.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 23.
dsPIC30F6010A/6015 23.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC30F6010A/6015 23.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 23.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
dsPIC30F6010A/6015 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to the “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below.
dsPIC30F6010A/6015 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6010A Max MIPS VDD Range (in Volts) Temp Range (in °C) dsPIC30F6010A-30I dsPIC30F6010A-20E 4.5-5.5 -40 to +85 30 — 4.5-5.5 -40 to +125 — 20 3.0-3.6 -40 to +85 20 — 3.0-3.6 -40 to +125 — 15 2.5-3.0 -40 to +85 10 — TABLE 24-2: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6015 Max MIPS VDD Range (in Volts) Temp Range (in °C) dsPIC30F6015-30I dsPIC30F6015-20E 4.5-5.5 -40 to +85 30 — 4.
dsPIC30F6010A/6015 TABLE 24-5: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units 2.5 — 5.5 V Industrial temperature Extended temperature Conditions Operating Voltage(2) DC10 VDD Supply Voltage DC11 VDD Supply Voltage 3.0 — 5.
dsPIC30F6010A/6015 TABLE 24-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC31a 9.5 15 mA 25°C DC31b 9.5 15 mA 85°C 3.3V DC31c 9.4 15 mA 125°C 0.
dsPIC30F6010A/6015 TABLE 24-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1,2) Max Units Conditions Operating Current (IDD)(3) DC51a 9.0 14 mA 25°C DC51b 9.0 14 mA 85°C 3.3V DC51c 9.0 14 mA 125°C 0.
dsPIC30F6010A/6015 TABLE 24-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units — μA Conditions Power-Down Current (IPD)(2) DC60a 0.2 25°C DC60b 1.2 40 μA 85°C DC60c 12 65 μA 125°C DC60e 0.4 — μA 25°C DC60f 1.
dsPIC30F6010A/6015 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.
dsPIC30F6010A/6015 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VOL DO10 Characteristic VOH DO20 Max Units Conditions — — 0.6 V IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V (RC or EC Osc mode) — — 0.72 V IOL = 2.
dsPIC30F6010A/6015 TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. BO10 Symbol VBOR Characteristic BOR Voltage(2) on VDD transition high-to-low Min Typ(1) Max Units — — — V BORV = 11(3) Conditions Not in operating range BORV = 10 2.6 — 2.71 V — BORV = 01 4.1 — 4.4 V — BORV = 00 4.58 — 4.
dsPIC30F6010A/6015 24.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 24-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Operating voltage VDD range as described in Table 24-1 and Table 24-2.
dsPIC30F6010A/6015 TABLE 24-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. OS10 Symb ol FOSC Characteristic External CLKN Frequency(2) (External clocks allowed only in EC mode) Oscillator Frequency(2) Min Typ(1) Max Units Conditions DC 4 4 4 — — — — 40 10 10 7.
dsPIC30F6010A/6015 TABLE 24-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Characteristic(1) Symbol Min Typ(2) Max Units Conditions OS50 FPLLI PLL Input Frequency Range(2) 4 4 4 4 4 4 5(3) 5(3) 5(3) 4 4 4 — — — — — — — — — — — — 10 10 7.5(4) 10 10 7.5(4) 10 10 7.5(4) 8.33(3) 8.33(3) 7.
dsPIC30F6010A/6015 TABLE 24-17: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator Mode EC XT Note 1: 2: 3: FOSC (MHz)(1) TCY (μsec)(2) MIPS(3) w/o PLL MIPS(3) w/PLL x4 MIPS(3) w/PLL x8 MIPS(3) w/PLL x16 0.200 20.0 0.05 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Assumption: Oscillator Postscaler is divide by 1. Instruction Execution Cycle Time: TCY = 1/MIPS.
dsPIC30F6010A/6015 TABLE 24-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1) OS63 Note 1: FRC — — ±2.00 % -40°C ≤TA ≤+85°C VDD = 3.0-5.5V — — ±5.00 % -40°C ≤TA ≤+125°C VDD = 3.0-5.5V Frequency is calibrated to 7.
dsPIC30F6010A/6015 FIGURE 24-4: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 24-2 for load conditions. TABLE 24-20: CLKOUT AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 FIGURE 24-5: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out OSC Time-out SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-2 for load conditions. DS70150E-page 192 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 TABLE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F6010A/6015 FIGURE 24-7: TIMER1, 2, 3, 4 AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRX Note: Refer to Figure 24-2 for load conditions. TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 TABLE 24-24: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 Symbol TtxH TtxL TtxP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Conditions Synchronous, no prescaler 0.
dsPIC30F6010A/6015 FIGURE 24-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ11 TQ10 TQ15 TQ20 POSCNT TABLE 24-26: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 FIGURE 24-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure 24-2 for load conditions. TABLE 24-27: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 FIGURE 24-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 24-29: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 FIGURE 24-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA/B MP20 PWMx FIGURE 24-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 24-2 for load conditions. TABLE 24-30: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 FIGURE 24-14: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ30 TQ31 TQ35 QEB (input) TQ41 TQ40 TQ30 TQ31 TQ35 QEB Internal TABLE 24-31: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 FIGURE 24-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Coun- TABLE 24-32: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol TQ50 TqIL TQ51 TQ55 Note 1: 2: Standard Operating Conditions: 2.5V to 5.
dsPIC30F6010A/6015 FIGURE 24-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 BIT14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb IN LSb IN BIT14 - - - -1 SP40 SP41 Note: Refer to Figure 24-2 for load conditions. TABLE 24-33: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F6010A/6015 FIGURE 24-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 SP40 SDIX LSb BIT14 - - - - - -1 MSb SDOX SP30,SP31 MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure 24-2 for load conditions. TABLE 24-34: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F6010A/6015 FIGURE 24-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb BIT14 - - - - - -1 SP51 SP30,SP31 SDIX MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure 24-2 for load conditions. SP40 TABLE 24-35: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
dsPIC30F6010A/6015 FIGURE 24-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP52 MSb SDOX BIT14 - - - - - -1 LSb SP30,SP31 SDIX MSb IN BIT14 - - - -1 SP51 LSb IN SP41 SP40 © 2011 Microchip Technology Inc. Note: Refer to Figure 24-2 for load conditions.
dsPIC30F6010A/6015 TABLE 24-36: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 FIGURE 24-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Stop Condition Start Condition Note: Refer to Figure 24-2 for load conditions. FIGURE 24-21: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure 24-2 for load conditions. © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 TABLE 24-37: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC30F6010A/6015 FIGURE 24-22: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS34 IS31 IS30 IS33 SDA Stop Condition Start Condition FIGURE 24-23: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 TABLE 24-38: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 Note Symbol TLO:SCL THI:SCL Characteristic Clock Low Time Clock High Time Min Max Units 100 kHz mode 4.7 — μs 400 kHz mode 1.
dsPIC30F6010A/6015 FIGURE 24-24: CXTX Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CXRX Pin (input) CA20 TABLE 24-39: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC30F6010A/6015 TABLE 24-40: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS(1) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply Greater of VDD – 0.3 or 2.7 — Lesser of VDD + 0.3 or 5.5 V — Vss - 0.3 — VSS + 0.
dsPIC30F6010A/6015 TABLE 24-40: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS(1) (CONTINUED) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
dsPIC30F6010A/6015 FIGURE 24-25: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution SET SAMP CLEAR SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 8 9 5 6 8 9 1 - Software sets ADCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17.
dsPIC30F6010A/6015 FIGURE 24-26: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) AD50 ADCLK Instruction Execution SET ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 TCONV AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADCON. ADON to start AD operation. 5 - Convert bit 0. 2 - Sampling starts after discharge period. TSAMP is described in Section 17.
dsPIC30F6010A/6015 TABLE 24-41: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max.
dsPIC30F6010A/6015 25.0 PACKAGING INFORMATION 25.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
dsPIC30F6010A/6015 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 64 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
dsPIC30F6010A/6015 ' ( !" #$ % & )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 80 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
dsPIC30F6010A/6015 ) ' ( # # !" #$ % & )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 80-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 b N NOTE 1 1 23 c φ β α NOTE 2 A A1 L L1 Units Dimension Limits Number of Leads A2 MILLIMETERS MIN N NOM MAX 80 Lead Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
dsPIC30F6010A/6015 )0 ' ( !" #$ * % & )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 NOTES: DS70150E-page 224 © 2011 Microchip Technology Inc.
dsPIC30F6010A/6015 APPENDIX A: REVISION HISTORY Revision A (July 2005) Original data sheet for dsPIC30F6010A/6015 devices. Revision B (September 2006) This revision reflects updates in these areas: • Data Ram protection feature enables segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security (see Section 3.2.
dsPIC30F6010A/6015 Revision E (March 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Section 15.0 “Motor Control PWM Module” Updated the PWM Period equations (see Equation 15-1 and Equation 15-2). Section 21.0 “System Integration” Added a shaded note on OSCTUN functionality in Section 21.2.
dsPIC30F6010A/6015 INDEX A A/D Aborting a Conversion ............................................. 143 Acquisition Requirements ........................................ 147 ADCHS .................................................................... 140 ADCON1 .................................................................. 140 ADCON2 .................................................................. 140 ADCON3 .................................................................. 140 ADCSSL ...................
dsPIC30F6010A/6015 Data EEPROM Read ................................................. 55 Data EEPROM Word Erase ....................................... 56 Data EEPROM Word Write ........................................ 57 Erasing a Row of Program Memory ........................... 51 Initiating a Programming Sequence ........................... 52 Loading Write Latches ............................................... 52 Port Write/Read Example .......................................... 60 Code Protection ...
dsPIC30F6010A/6015 Register Map (dsPIC30F6015) .................................. 47 Interrupt Priority ................................................................. 42 Interrupt Sequence ............................................................ 45 Interrupt Stack Frame ................................................ 45 Interrupts ............................................................................ 41 I2C Master Operation Baud Rate Generator ...............................................
dsPIC30F6010A/6015 PWM Special Event Trigger ............................................. 106 Postscaler ................................................................ 106 PWM Time Base ................................................................ 99 Continuous Up/Down Counting Modes ...................... 99 Double Update Mode ............................................... 100 Free-Running Mode ................................................... 99 Postscaler ........................................
dsPIC30F6010A/6015 10-bit High-Speed A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) ........... 216 10-bit High-Speed A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) ............................................... 217 Timing Requirements Input Capture ........................................................... 199 Timing Specifications Band Gap Start-up Time Requirements ................... 195 CAN I/O Requirements ............................................
dsPIC30F6010A/6015 NOTES: DS70150E-page 232 © 2011 Microchip Technology Inc.
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