Datasheet

© 2011 Microchip Technology Inc. DS70149E-page 93
dsPIC30F5015/5016
14.4 Programmable Digital Noise Filters
The digital noise filter section is responsible for reject-
ing noise on the incoming quadrature signals. Schmitt
Trigger inputs and a three-clock cycle delay filter com-
bine to reject low-level noise and large, short duration
noise spikes that typically occur in noise prone applica-
tions, such as a motor system.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been
registered for three consecutive clock cycles.
For the QEA, QEB and INDX pins, the clock divide
frequency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>) and are derived from
the base instruction cycle T
CY.
To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for
all channels is disabled on POR and BOR.
14.5 Alternate 16-bit Timer/Counter
When the QEI module is not configured for the QEI
mode, QEIM<2:0> = 001, the module can be config-
ured as a simple 16-bit timer/counter. The setup and
control of the auxiliary timer is accomplished through
the QEICON SFR register. This timer functions
identically to Timer1. The QEA pin is used as the timer
clock input.
When configured as a timer, the POSCNT register
serves as the Timer Count register and the MAXCNT
register serves as the Period register. When a Timer/
Period register match occurs, the QEI interrupt flag will
be asserted.
The only exception between the general purpose tim-
ers and this timer is the added feature of external up/
down input select. When the UPDN pin is asserted
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.
The UPDN control/Status bit (QEICON<11>) can be
used to select the count direction state of the Timer
register. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.
In addition, control bit, UDSRC (QEICON<0>), deter-
mines whether the timer count direction state is based
on the logic state written into the UPDN control/Status
bit (QEICON<11>), or the QEB pin state. When
UDSRC = 1, the timer count direction is controlled from
the QEB pin. Likewise, when UDSRC = 0, the timer
count direction is controlled by the UPDN bit.
14.6 QEI Module Operation During CPU
Sleep Mode
14.6.1 QEI OPERATION DURING CPU
SLEEP MODE
The QEI module will be halted during the CPU Sleep
mode.
14.6.2 TIMER OPERATION DURING CPU
SLEEP MODE
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
14.7 QEI Module Operation During CPU
Idle Mode
Since the QEI module can function as a Quadrature
Encoder Interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
14.7.1 QEI OPERATION DURING CPU IDLE
MODE
When the CPU is placed in the Idle mode, the QEI mod-
ule will operate if the QEISIDL bit (QEICON<13>) = 0.
This bit defaults to a logic ‘0’ upon executing POR and
BOR. For halting the QEI module during the CPU Idle
mode, QEISIDL should be set to ‘1’.
14.7.2 TIMER OPERATION DURING CPU
IDLE MODE
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if the QEISIDL bit (QEI-
CON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been
entered.
Note: Changing the operational mode (i.e., from
QEI to Timer or vice versa), will not affect
the Timer/Position Count register contents.
Note: This timer does not support the External
Asynchronous Counter mode of operation.
If using an external clock source, the clock
will automatically be synchronized to the
internal instruction cycle.