Datasheet

dsPIC30F5015/5016 DS70149E-page 164 © 2011 Microchip Technology Inc.
TABLE 21-7: SYSTEM INTEGRATION REGISTER MAP
(1)
TABLE 21-8: DEVICE CONFIGURATION REGISTER MAP
(1)
SFR
Name
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
RCON 0740 TRAPR IOPUWR BGST
— — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset.
OSCCON 0742
— COSC<2:0> — NOSC<2:0> POST<1:0> LOCK —CF— LPOSCEN OSWEN Depends on Configuration bits.
OSCTUN
0744
— — — — — — — — — — — TUN<4:0> 0000 0000 0000 0000
PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD PWMMD
— I2CMD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD
0000 0000 0000 0000
PMD2 0772
— — — —
IC4MD IC3MD IC2MD IC1MD
— — — —
OC4MD OC3MD OC2MD OC1MD
0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FOSC F80000 FCKSM<1:0>
— — —FOS<2:0>— — — FPR<4:0>
FWDT F80002 FWDTEN
— — — — — — — — — FWPSA<1:0> FWPSB<3:0>
FBORPOR F80004 MCLREN
— — — — PWMPIN HPOL LPOL BOREN —BORV<1:0>— —FPWRT<1:0>
FBS F80006
— — Reserved
(2)
— — — Reserved
(2)
— — — — Reserved
(2)
FSS F80008 — — Reserved
(2)
— — Reserved
(2)
— — — — Reserved
(2)
FGS F8000A — — — — — — — — — — — — — Reserved
(3)
GCP GWRP
FICD F8000C BKBUG COE
— — — — — — — — — — — —ICS<1:0>
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2: Reserved bits read as ‘1’ and must be programmed as ‘1’.
3: The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).