Datasheet

dsPIC30F5015/5016
DS70149E-page 146 © 2011 Microchip Technology Inc.
20.8 ADC Acquisition Requirements
The analog input model of the 10-bit ADC is shown in
Figure 20-3. The total sampling time for the ADC is a
function of the internal amplifier settling time, device
V
DD and the holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
HOLD) must be allowed to fully
charge to the voltage level on the analog input pin. The
analog output source impedance (R
S), the interconnect
impedance (RIC), and the internal sampling switch
(RSS) impedance combine to directly affect the time
required to charge the capacitor C
HOLD. The combined
impedance must therefore be small enough to fully
charge the holding capacitor within the chosen sample
time. To minimize the effects of pin leakage currents on
the accuracy of the ADC, the maximum recommended
source impedance, R
S, is 5 kΩ for conversion rates up
to 500 ksps and a maximum of 500Ω for conversion
rates up to 1 Msps. After the analog input channel is
selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
The user must allow at least 1 T
AD period of sampling
time, TSAMP, between conversions to allow each sam-
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the ADC. In an
automatic configuration, the user must allow enough
time between conversion triggers so that the minimum
sample time can be satisfied. Refer to Table 24-40 for
T
AD and sample time requirements.
FIGURE 20-3: ADC CONVERTER ANALOG INPUT MODEL
CPIN
VA
Rs
ANx
V
T = 0.6V
V
T = 0.6V
I leakage
R
IC ≤ 250Ω
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 4.4 pF
± 500 nA
Legend: CPIN
VT
I leakage
RIC
RSS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
RSS ≤ 3 kΩ