Datasheet
dsPIC30F5015/5016
DS70149E-page 144 © 2011 Microchip Technology Inc.
The configuration guidelines give the required setup
values for the conversion speeds above 500 ksps,
since they require external VREF pins usage and there
are some differences in the configuration procedure.
Configuration details that are not critical to the
conversion speed have been omitted.
The following figure depicts the recommended circuit
for the conversion rates above 500 ksps.
FIGURE 20-2: ADC VOLTAGE REFERENCE SCHEMATIC
20.7.1 1 Msps CONFIGURATION
GUIDELINE
The configuration for 1 Msps operation is dependent on
whether a single input pin is to be sampled or whether
multiple pins will be sampled.
20.7.1.1 Single Analog Input
For conversions at 1 Msps for a single analog input, at
least two sample and hold channels must be enabled.
The analog input multiplexer must be configured so
that the same input pin is connected to both sample
and hold channels. The ADC converts the value held
on one S/H channel, while the second S/H channel
acquires a new input sample.
20.7.1.2 Multiple Analog Inputs
The ADC can also be used to sample multiple analog
inputs using multiple sample and hold channels. In this
case, the total 1 Msps conversion rate is divided among
the different input signals. For example, four inputs can
be sampled at a rate of 250 ksps for each signal or two
inputs could be sampled at a rate of 500 ksps for each
signal. Sequential sampling must be used in this con-
figuration to allow adequate sampling time on each
input.
V
DD
V
DD
V
DD
R2
10
C2
0.1
μ
F
C1
0.01
μ
F
R1
10
C8
1 mF
V
DD
C7
0.1 mF
V
DD
C6
0.01 mF
V
DD
C5
1 mF
V
DD
C4
0.1 mF
V
DD
C3
0.01 mF
dsPIC30F5015
1
2
3
4
5
6
MCLR
8
V
SS
VDD
11
12
13
36
35
34
33
32
31
30
29
28
27
V
DD
64
63
62
61
60
59
58
V
DD
VSS
14
V
REF-
V
REF+
17
18
AV
DD
AVSS
21
22
23
24
V
SS
AVDD
VDD
43
42
V
SS
40
39
V
DD
37
44
48
47
46
50
49
51
54
53
52
55
45
V
DD
VDD