Datasheet

© 2011 Microchip Technology Inc. DS70149E-page 103
dsPIC30F5015/5016
15.7.2 DEAD-TIME ASSIGNMENT
The DTCON2 SFR contains control bits that allow the
dead times to be assigned to each of the complemen-
tary outputs. Table 15-1 summarizes the function of
each dead-time selection control bit.
TABLE 15-1: DEAD-TIME SELECTION BITS
15.7.3 DEAD-TIME RANGES
The amount of dead time provided by each dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value. The amount of dead
time provided by each unit may be set independently.
Four input clock prescaler selections have been pro-
vided to allow a suitable range of dead times, based on
the device operating frequency. The clock prescaler
option may be selected independently for each of the
two dead-time values. The dead-time clock prescaler
values are selected using the DTAPS<1:0> and
DTBPS<1:0> control bits in the DTCON1 SFR. One of
four clock prescaler options (T
CY, 2 TCY, 4 TCY or 8 TCY)
may be selected for each of the dead-time values.
After the prescaler values are selected, the dead time
for each unit is adjusted by loading two 6-bit unsigned
values into the DTCON1 SFR.
The dead-time unit prescalers are cleared on the
following events:
• On a load of the down timer due to a duty cycle
comparison edge event.
• On a write to the DTCON1 or DTCON2 registers.
• On any device Reset.
FIGURE 15-4: DEAD-TIME TIMING DIAGRAM
Bit Selects
DTS1A PWM1L/PWM1H active edge dead time.
DTS1I PWM1L/PWM1H inactive edge dead time.
DTS2A PWM2L/PWM2H active edge dead time.
DTS2I PWM2L/PWM2H inactive edge dead time.
DTS3A PWM3L/PWM3H active edge dead time.
DTS3I PWM3L/PWM3H inactive edge dead time.
DTS4A PWM4L/PWM4H active edge dead time.
DTS4I PWM4L/PWM4H inactive edge dead time.
Note: The user should not modify the DTCON1
or DTCON2 values while the PWM mod-
ule is operating (PTEN = 1). Unexpected
results may occur.
Duty Cycle Generator
PWMxH
PWMxL
Time selected by DTSxA bit (A or B) Time selected by DTSxI bit (A or B)