Datasheet

dsPIC30F5015/5016
DS70149E-page 102 © 2011 Microchip Technology Inc.
15.5.1 DUTY CYCLE REGISTER BUFFERS
The four PWM Duty Cycle registers are double-buffered
to allow glitchless updates of the PWM outputs. For each
duty cycle, there is a Duty Cycle register that is accessi-
ble by the user, and a second Duty Cycle register that
holds the actual compare value used in the present
PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER reg-
ister occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is dis-
abled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
15.5.2 DUTY CYCLE IMMEDIATE
UPDATES
When the Immediate Update Enable bit is set (IUE = 1),
any write to the Duty Cycle registers updates the new
duty cycle value immediately. This feature gives the
option to the user to allow immediate updates of the
active PWM Duty Cycle registers instead of waiting for
the end of the current time base period. System stabil-
ity is improved in closed-loop servo applications by
reducing the delay between system observation and
the issuance of system corrective commands when
immediate updates are enabled.
If the PWM output is active at the time the new duty
cycle is written, and the new duty cycle is less than the
current time base value, the PWM pulse width is
shortened.
If the PWM output is active at the time the new duty
cycle is written, and the new duty cycle is greater than
the current time base value, the PWM pulse width is
lengthened.
If the PWM output is inactive at the time the new duty
cycle is written, and the new duty cycle is greater than
the current time base value, the PWM output becomes
active immediately and remains active for the new
written duty cycle value.
15.6 Complementary PWM Operation
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead time may be optionally inserted during
device switching, when both outputs are inactive for a
short period (Refer to Section 15.7 “Dead-Time
Generators”).
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
• PDC1 register controls PWM1H/PWM1L outputs
• PDC2 register controls PWM2H/PWM2L outputs
• PDC3 register controls PWM3H/PWM3L outputs
• PDC4 register controls PWM4H/PWM4L outputs
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to
Complementary mode by default upon a device Reset.
15.7 Dead-Time Generators
Dead-time generation may be provided when any of the
PWM I/O pin pairs are operating in the Complementary
Output mode. The PWM outputs use Push-Pull drive cir-
cuits. Due to the inability of the power output devices to
switch instantaneously, some amount of time must be
provided between the turn off event of one PWM output
in a complementary pair and the turn on event of the
other transistor.
The PWM module allows two different dead times to be
programmed. These two dead times may be used in
one of two methods described below to increase user
flexibility:
• The PWM output signals can be optimized for
different turn off times in the high side and low
side transistors in a complementary pair of tran-
sistors. The first dead time is inserted between
the turn off event of the lower transistor of the
complementary pair and the turn on event of the
upper transistor. The second dead time is inserted
between the turn off event of the upper transistor
and the turn on event of the lower transistor.
• The two dead times can be assigned to individual
PWM I/O pin pairs. This operating mode allows
the PWM module to drive different transistor/load
combinations with each complementary PWM I/O
pin pair.
15.7.1 DEAD-TIME GENERATORS
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 15-4, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.