Datasheet

dsPIC30F5011/5013
DS70116J-page 28 © 2011 Microchip Technology Inc.
3.2 Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1 DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64-
Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64 Kbyte data address
space excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.
The MAC class instructions extract the Y address space
from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.
The data space memory map is shown in Figure 3-6.
The X data space is used by all instructions and supports
all addressing modes, as shown in Figure 3-7.
FIGURE 3-6: DATA SPACE MEMORY MAP
0x0000
0x07FE
0x0FFE
0xFFFE
LSB
Address
16 bits
LSBMSB
MSB
Address
0x0001
0x07FF
0x0FFF
0xFFFF
0x8001
0x8000
Optionally
Mapped
into Program
Memory
0x17FF 0x17FE
0x18000x1801
0x0801
0x0800
0x1001 0x1000
Near
Data
0x1FFE 0x1FFF
2 Kbyte
SFR Space
4 Kbyte
SRAM Space
8 Kbyte
Space
X Data
Unimplemented (X)
SFR Space
X Data RAM (X)
Y Data RAM (Y)