Datasheet

dsPIC30F5011/5013
DS70116J-page 214 © 2011 Microchip Technology Inc.
Output Compare Sleep Mode Operation............................. 84
P
Packaging Information ...................................................... 203
Marking ..................................................................... 203
Peripheral Module Disable (PMD) Registers .................... 149
Pinout Descriptions ............................................................. 12
PLL Clock Timing Specifications....................................... 175
POR. See Power-on Reset.
Port Write/Read Example.................................................... 58
PORTA
Register Map for dsPIC30F5013 ................................ 59
PORTB
Register Map for dsPIC30F5011/5013 ....................... 59
PORTC
Register Map for dsPIC30F5011 ................................ 59
Register Map for dsPIC30F5013 ................................ 59
PORTD
Register Map for dsPIC30F5011 ................................ 60
Register Map for dsPIC30F5013 ................................ 60
PORTF
Register Map for dsPIC30F5011 ................................ 60
Register Map for dsPIC30F5013 ................................ 61
PORTG
Register Map for dsPIC30F5011/5013 ....................... 61
Power Saving Modes ........................................................ 147
Idle ............................................................................ 148
Sleep......................................................................... 147
Sleep and Idle ........................................................... 137
Power-Down Current (I
PD) ................................................ 168
Power-up Timer
Timing Characteristics .............................................. 178
Timing Requirements................................................ 179
Program Address Space ..................................................... 23
Construction................................................................ 24
Data Access from Program Memory Using Program
Space Visibility.................................................... 26
Data Access From Program Memory Using Table In-
structions............................................................. 25
Data Access from, Address Generation...................... 24
Data Space Window into Operation............................ 27
Data Table Access (LS Word) .................................... 25
Data Table Access (MS Byte)..................................... 26
Memory Map ............................................................... 23
Table Instructions
TBLRDH.............................................................. 25
TBLRDL .............................................................. 25
TBLWTH ............................................................. 25
TBLWTL.............................................................. 25
Program and EEPROM Characteristics ............................ 172
Program Counter................................................................. 16
Programmable................................................................... 137
Programmer’s Model........................................................... 16
Diagram ...................................................................... 17
Programming Operations .................................................... 49
Algorithm for Program Flash ....................................... 49
Erasing a Row of Program Memory ............................ 49
Initiating the Programming Sequence......................... 50
Loading Write Latches ................................................ 50
Protection Against Accidental Writes to OSCCON ........... 142
R
Reader Response ............................................................. 216
Reset......................................................................... 137, 143
BOR, Programmable................................................. 145
Brown-out Reset (BOR) ............................................ 137
Oscillator Start-up Timer (OST) ................................ 137
POR
Operating without FSCM and PWRT................ 145
With Long Crystal Start-up Time ...................... 145
POR (Power-on Reset)............................................. 143
Power-on Reset (POR)............................................. 137
Power-up Timer (PWRT) .......................................... 137
Reset Sequence ................................................................. 37
Reset Sources ............................................................ 37
Reset Sources
Brown-out Reset (BOR).............................................. 37
Illegal Instruction Trap ................................................ 37
Trap Lockout............................................................... 37
Uninitialized W Register Trap ..................................... 37
Watchdog Time-out .................................................... 37
Reset Timing Characteristics............................................ 178
Reset Timing Requirements ............................................. 179
Run-Time Self-Programming (RTSP) ................................. 47
S
Simple Capture Event Mode............................................... 77
Buffer Operation ......................................................... 78
Hall Sensor Mode ....................................................... 78
Prescaler .................................................................... 77
Timer2 and Timer3 Selection Mode............................ 78
Simple OC/PWM Mode Timing Requirements ................. 185
Simple Output Compare Match Mode ................................ 82
Simple PWM Mode ............................................................. 82
Input Pin Fault Protection ........................................... 82
Period ......................................................................... 83
Software Simulator (MPLAB SIM) .................................... 161
Software Stack Pointer, Frame Pointer .............................. 16
CALL Stack Frame ..................................................... 31
SPI Module ......................................................................... 87
Framed SPI Support................................................... 87
Operating Function Description .................................. 87
Operation During CPU Idle Mode ............................... 89
Operation During CPU Sleep Mode............................ 89
SDOx Disable ............................................................. 87
Slave Select Synchronization ..................................... 89
SPI1 Register Map...................................................... 90
SPI2 Register Map...................................................... 90
Timing Characteristics
Master Mode (CKE = 0).................................... 189
Master Mode (CKE = 1).................................... 190
Slave Mode (CKE = 1).............................. 191, 192
Timing Requirements
Master Mode (CKE = 0).................................... 189
Master Mode (CKE = 1).................................... 190
Slave Mode (CKE = 0)...................................... 191
Slave Mode (CKE = 1)...................................... 193
Word and Byte Communication .................................. 87
Status Bits, Their Significance and the Initialization Condition
for RCON Register, Case 1 ...................................... 146
Status Bits, Their Significance and the Initialization Condition
for RCON Register, Case 2 ...................................... 146
Status Register ................................................................... 16
Symbols Used in Opcode Descriptions ............................ 152
System Integration............................................................ 137
Register Map ............................................................ 150
T
Table Instruction Operation Summary ................................ 47
Temperature and Voltage Specifications
AC............................................................................. 173
Timer1 Module.................................................................... 63