Datasheet

dsPIC30F5011/5013
DS70116J-page 212 © 2011 Microchip Technology Inc.
Overflow and Saturation ............................................. 20
Round Logic................................................................ 21
Write Back................................................................... 21
Data Address Space ........................................................... 28
Alignment .................................................................... 30
Alignment (Figure) ...................................................... 30
Effect of Invalid Memory Accesses (Table)................. 30
MCU and DSP (MAC Class) Instructions Example..... 29
Memory Map ............................................................... 28
Near Data Space ........................................................ 31
Software Stack............................................................ 31
Spaces ........................................................................ 30
Width........................................................................... 30
Data Converter Interface (DCI) Module ............................ 117
Data EEPROM Memory ...................................................... 53
Erasing........................................................................ 54
Erasing, Block ............................................................. 54
Erasing, Word ............................................................. 54
Protection Against Spurious Write .............................. 56
Reading....................................................................... 53
Write Verify ................................................................. 56
Writing......................................................................... 55
Writing, Block .............................................................. 56
Writing, Word .............................................................. 55
DC Characteristics ............................................................ 164
BOR .......................................................................... 172
Brown-out Reset ....................................................... 171
I/O Pin Output Specifications .................................... 170
Idle Current (I
IDLE) .................................................... 167
Low-Voltage Detect................................................... 170
LVDL ......................................................................... 171
Operating Current (I
DD)............................................. 165
Power-Down Current (I
PD) ........................................ 168
Program and EEPROM............................................. 172
Temperature and Voltage Specifications .................. 165
DCI Module
Bit Clock Generator................................................... 121
Buffer Alignment with Data Frames .......................... 123
Buffer Control............................................................ 117
Buffer Data Alignment............................................... 117
Buffer Length Control................................................ 123
COFS Pin.................................................................. 117
CSCK Pin.................................................................. 117
CSDI Pin ................................................................... 117
CSDO Mode Bit ........................................................ 124
CSDO Pin ................................................................. 117
Data Justification Control Bit..................................... 122
Device Frequencies for Common Codec CSCK Frequen-
cies (Table) ....................................................... 121
Digital Loopback Mode ............................................. 124
Enable....................................................................... 119
Frame Sync Generator ............................................. 119
Frame Sync Mode Control Bits ................................. 119
I/O Pins ..................................................................... 117
Interrupts................................................................... 124
Introduction ............................................................... 117
Master Frame Sync Operation.................................. 119
Operation .................................................................. 119
Operation During CPU Idle Mode ............................. 124
Operation During CPU Sleep Mode .......................... 124
Receive Slot Enable Bits........................................... 122
Receive Status Bits................................................... 123
Register Map............................................................. 126
Sample Clock Edge Control Bit................................. 122
Slave Frame Sync Operation.................................... 119
Slot Enable Bits Operation with Frame Sync............ 122
Slot Status Bits ......................................................... 124
Synchronous Data Transfers .................................... 122
Timing Characteristics
AC-Link Mode................................................... 188
Multichannel, I
2
S Modes................................... 186
Timing Requirements
AC-Link Mode................................................... 188
Multichannel, I
2
S Modes................................... 187
Transmit Slot Enable Bits ......................................... 122
Transmit Status Bits.................................................. 123
Transmit/Receive Shift Register ............................... 117
Underflow Mode Control Bit...................................... 124
Word Size Selection Bits .......................................... 119
Development Support ....................................................... 159
Device Configuration
Register Map ............................................................ 150
Device Configuration Registers
FBORPOR................................................................ 148
FBS........................................................................... 148
FGS .......................................................................... 148
FOSC........................................................................ 148
FSS........................................................................... 148
FWDT ....................................................................... 148
Device Overview................................................................... 9
Disabling the UART .......................................................... 101
Divide Support .................................................................... 18
Instructions (Table)..................................................... 18
DSP Engine ........................................................................ 18
Multiplier ..................................................................... 20
Dual Output Compare Match Mode .................................... 82
Continuous Pulse Mode.............................................. 82
Single Pulse Mode...................................................... 82
E
Electrical Characteristics .................................................. 163
AC............................................................................. 173
DC ............................................................................ 164
Enabling and Setting Up UART
Setting Up Data, Parity and Stop Bit Selections....... 101
Enabling the UART ........................................................... 101
Equations
ADC Conversion Clock ............................................. 129
Baud Rate................................................................. 103
Bit Clock Frequency.................................................. 121
COFSG Period.......................................................... 119
Serial Clock Rate........................................................ 96
Time Quantum for Clock Generation ........................ 113
Errata .................................................................................... 7
Exception Sequence
Trap Sources .............................................................. 37
External Clock Timing Characteristics
Type A, B and C Timer ............................................. 181
External Clock Timing Requirements ............................... 174
Type A Timer ............................................................ 181
Type B Timer ............................................................ 182
Type C Timer ............................................................ 182
External Interrupt Requests ................................................ 39
F
Fast Context Saving ........................................................... 39
Flash Program Memory ...................................................... 47
I
I/O Ports.............................................................................. 57
Parallel (PIO) .............................................................. 57