Datasheet

dsPIC30F5011/5013
DS70116J-page 150 © 2011 Microchip Technology Inc.
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP
(1)
TABLE 20-8: DEVICE CONFIGURATION REGISTER MAP
(1)
SFR
Name
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
RCON 0740 TRAPR IOPUWR BGST LVDEN LVDL<3:0> EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 2) OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 TUN0 NOSC<1:0> POST<1:0> LOCK
—CF— LPOSCEN OSWEN (Note 23
PMD1 0770 T5MD T4MD T3MD T2MD T1MD
— — DCIMD I2CMD U2MD U1MD SPI2MD SPI1MD C2MD C1MD ADCMD 0000 0000 0000 0000
PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 0000 0000 0000 Legend: — = unimplemented, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2: Reset state depends on type of Reset. 3: Reset state depends on Configuration bits.
Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FOSC F80000 FCKSM<1:0>
— — — —FOS<1:0>— — — —FPR<3:0>
FWDT F80002 FWDTEN
— — — — — — — — — FWPSA<1:0> FWPSB<3:0>
FBORPOR F80004 MCLREN
— — — — Reserved
(2)
BOREN — BORV<1:0> — —FPWRT<1:0>
FBS F80006
— — RBS<1:0> — — —
EBS
— — — —
BSS<2:0>
BWRP
FSS F80008
— — RSS<1:0> — — ESS<1:0> — — — —
SSS<2:0>
SWRP
FGS F8000A
— — — — — — — — — — — — —GSS<1:0>GWRP
FICD F8000C BKBUG COE
— — — — — — — — — — — —ICS<1:0>
Legend: — = unimplemented, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2: Reserved bits read as ‘1’ and must be programmed as ‘1’.