Datasheet

dsPIC30F5011/5013
DS70116J-page 148 © 2011 Microchip Technology Inc.
Any interrupt that is individually enabled (using the cor-
responding IE bit), and meets the prevailing priority level
will be able to wake-up the processor. The processor will
process the interrupt and branch to the ISR. The Sleep
Status bit in the RCON register is set upon wake-up.
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the Sleep
Status bit. In a POR, the Sleep bit is cleared.
If the Watchdog Timer is enabled, then the processor
will wake-up from Sleep mode upon WDT time-out. The
SLEEP and WDTO Status bits are both set.
20.6.2 IDLE MODE
In Idle mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module
that allows them to operate during Idle.
LPRC Fail-Safe Clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions has occurred:
• Any interrupt that is individually enabled (IE bit is
‘1’) and meets the required priority level
• Any Reset (POR, BOR, MCLR
)
• A WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins immedi-
ately, starting with the instruction following the PWRSAV
instruction.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle Status bit in
the RCON register is set upon wake-up.
Any Reset other than POR will set the Idle Status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
20.7 Device Configuration Registers
The Configuration bits in each device Configuration
register specify some of the Device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are seven
device Configuration registers available to the user:
•F
OSC (0xF80000): Oscillator Configuration
Register
• FWDT (0xF80002): Watchdog Timer
Configuration Register
• FBORPOR (0xF80004): BOR and POR
Configuration Register
• FBS (0xF80006): Boot Code Segment
Configuration Register
• FSS (0xF80008): Secure Code Segment
Configuration Register
• FGS (0xF8000A): General Code Segment
Configuration Register
• FICD (0xF8000C): Debug Configuration
Register
The placement of the Configuration bits is automati-
cally handled when you select the device in your device
programmer. The desired state of the Configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming inter-
face. After the device has been programmed, the appli-
cation software may read the Configuration bit values
through the table read instructions. For additional infor-
mation, please refer to the “dsPIC30F Flash Program-
ming Specification” (DS70102), the “dsPIC30F Family
Reference Manual” (DS70046) and the “CodeGuard™
Security” chapter (DS70180).
Note: In spite of various delays applied (T
POR,
T
LOCK and TPWRT), the crystal oscillator
(and PLL) may not be active at the end of
the time-out (e.g., for low frequency crys-
tals). In such cases, if FSCM is enabled,
then the device will detect this as a clock
failure and process the clock failure trap,
the FRC oscillator will be enabled and the
user will have to re-enable the crystal oscil-
lator. If FSCM is not enabled, then the
device will simply suspend execution of
code until the clock is stable and will remain
in Sleep until the oscillator clock has
started.
Note: 1. If the code protection configuration fuse
bits (FBS<BSS<2:0>, FSS<SSS<2:0>,
FGS<GCP> and FGS<GWRP>) have
been programmed, an erase of the entire
code-protected device is only possible at
voltages V
DD ≥ 4.5V.
2. This device supports an Advanced
implementation of CodeGuard™ Security.
Please refer to the “CodeGuard Security”
chapter (DS70180) for information on how
CodeGuard Security may be used in your
application.