Datasheet

dsPIC30F5011/5013
DS70116J-page 132 © 2011 Microchip Technology Inc.
FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 TAD
SAMPLING TIME
19.8 ADC Acquisition Requirements
The analog input model of the 12-bit ADC is shown in
Figure 19-4. The total sampling time for the ADC is a
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
HOLD) must be allowed to fully
charge to the voltage level on the analog input pin. The
source impedance (R
S), the interconnect impedance
(RIC), and the internal sampling switch (RSS) imped-
ance combine to directly affect the time required to
charge the capacitor C
HOLD. The combined impedance
of the analog sources must therefore be small enough
to fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage cur-
rents on the accuracy of the ADC, the maximum rec-
ommended source impedance, R
S, is 2.5 kΩ. After the
analog input channel is selected (changed), this sam-
pling function must be completed prior to starting the
conversion. The internal holding capacitor will be in a
discharged state prior to each sample operation.
FIGURE 19-4: 12-BIT ADC ANALOG INPUT MODEL
TCONV
= 14 TAD
TSAMP
= 1 TAD
TSAMP
= 1 TAD
ADCLK
SAMP
DONE
ADCBUF0
ADCBUF1
Instruction Execution BSET ADCON1, ASAM
TCONV
= 14 TAD
CPIN
VA
Rs
ANx
V
T = 0.6V
V
T = 0.6V
I leakage
R
IC ≤ 250Ω
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 18 pF
± 500 nA
Legend: CPIN
VT
I leakage
R
IC
RSS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ.
RSS ≤ 3 kΩ