Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 80 (12x12) 16-Bit 30 null I/O number 68

dsPIC30F5011/5013

Data Sheet

High-Performance,

16-bit Digital Signal Controllers

Summary of content (220 pages)

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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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dsPIC30F5011/5013 High-Performance, Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F5011/5013 CMOS Technology: • • • • Low-power, high-speed Flash technology Wide operating voltage range (2.5V to 5.
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dsPIC30F5011/5013 Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC30F5011 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC2/OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKI V
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dsPIC30F5011/5013 Pin Diagrams (Continued) IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD1 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 OC7/CN15/RD6 CSCK/RG14 CN23/RA7 CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/RD7 CSDI/RG12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CSDO/RG13 80-Pin TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 T4CK/RC3 T5CK/RC4 SCK2/CN8/RG6 4 5 6 60 EMUC1/SOSCO/T1CK/CN0/RC14 59 EMUD1/SOSCI/CN1/RC13 58 EMUC2/OC1/RD0 57 56 IC4/RD11 IC3/RD10 55 IC2/R
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dsPIC30F5011/5013 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU Architecture Overview........................................................................................................................................................ 15 3.0 Memory Organization ..........................................................................
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dsPIC30F5011/5013 1.0 Note: DEVICE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F5011/5013 FIGURE 1-1: dsPIC30F5011 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Interrupt Controller PSV & Table Data Access 24 Control Block 8 AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 16 X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Address Latch Program Memory (66 Kbyte
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dsPIC30F5011/5013 FIGURE 1-2: dsPIC30F5013 BLOCK DIAGRAM Y Data Bus PSV & Table Data Access 24 Control Block 8 Address Latch Data EEPROM (1 Kbyte) 16 PORTA X RAGU X WAGU Y AGU PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Program Memory (66 Kbytes) 16 Data Latch Data Latch X Data Y Data RAM RAM (2 Kbytes) (2 Kbytes) Address Address Latch Latch 16 16 16 16 24 24 16 16 16 Interrupt Controller CN22/RA6 CN23/RA7 VREF-/RA9 VREF+/RA10 INT1/RA12 INT2/RA13 INT3/RA14 INT4/RA15
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dsPIC30F5011/5013 Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN15 I Analog Analog input channels. AN0 and AN1 are also used for device programming data and clock inputs, respectively.
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dsPIC30F5011/5013 TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type Description OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. OSC2 I/O PGD PGC I/O I ST ST In-Circuit Serial Programming™ data input/output pin. In-Circuit Serial Programming clock input pin.
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dsPIC30F5011/5013 2.0 Note: 2.1 CPU ARCHITECTURE OVERVIEW This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F5011/5013 The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors.
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dsPIC30F5011/5013 FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
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dsPIC30F5011/5013 2.3 Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: • • • • • DIVF - 16/16 signed fractional divide DIV.sd - 32/16 signed divide DIV.ud - 32/16 unsigned divide DIV.sw - 16/16 signed divide DIV.
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dsPIC30F5011/5013 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In 40 Saturate S a Round t 16 u Logic r a t e Adder Negate 40 40 40 Barrel Shifter 16 X Data Bus 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 2.4.1 MULTIPLIER The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits.
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dsPIC30F5011/5013 The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred.
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dsPIC30F5011/5013 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.
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dsPIC30F5011/5013 Note: 3.1 MEMORY ORGANIZATION FIGURE 3-1: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F5011/5013 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> Instruction Access User TBLRD/TBLWT User (TBLPAG<7> = 0) TBLPAG<7:0> Data EA<15:0> TBLRD/TBLWT Configuration (TBLPAG<7> = 1) TBLPAG<7:0> Data EA<15:0> Program Space Visibility User FIGURE 3-2: <0> PC<22:1> 0 0 PSVPAG<7:0> 0 Data EA<14:0> DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program Counter Program Counter 0 Select Us
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dsPIC30F5011/5013 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS A set of table instructions are provided to move byte or word sized data to and from program space. 1. This architecture fetches 24-bit wide program memory. Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space.
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dsPIC30F5011/5013 FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) TBLRDH.W PC Address 0x000000 0x000002 0x000004 0x000006 23 16 8 0 00000000 00000000 00000000 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 TBLRDH.B (Wn<0> = 1) DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page.
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dsPIC30F5011/5013 FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x000100 0x0000 EA<15> = 0 PSVPAG(1) 0x01 8 15 Data 16 Space 15 EA EA<15> = 1 0x8000 15 Address Concatenation 23 23 15 0 0x008000 Upper Half of Data Space is Mapped into Program Space 0x017FFF 0xFFFF BSET MOV MOV MOV Note: CORCON,#2 #0x01, W0 W0, PSVPAG 0x8000, W0 ; PSV bit set ; Set PSVPAG register ; Access program memory location ; using a data space access Data Read PSVPAG is an 8-b
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dsPIC30F5011/5013 3.2 Data Address Space The core has two data spaces. The data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. 3.2.1 DATA SPACE MEMORY MAP The data space memory is split into two blocks, X and Y data space.
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dsPIC30F5011/5013 DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE X SPACE FIGURE 3-7: Y SPACE UNUSED X SPACE (Y SPACE) X SPACE UNUSED UNUSED Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 3.2.2 DATA SPACES 3.2.3 X data space is used by all instructions and supports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions (MAC class). The X write data bus is the only write path to data space for all instructions.
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dsPIC30F5011/5013 All byte loads into any W register are loaded into the LSB. The MSB is not modified. A sign-extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.
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DS70116J-page 32 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 0022 W7 W8 W9 W10 W11 W12 W13 W14 W15 SPLIM ACCAL — — — — — — — — — — — — — — — — — — Bit 7 — — — PCL ACCBH ACCBL ACCAH ACCAL SPLIM W15 W14 W13 W12 W11 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 — W0 / WREG Bit 8 003E 0040 0042 DOENDL DOENDH SR OA — — OB — — SA — — SB — — OAB — — SAB — — DA — — DC — DOENDL — DOSTARTL IPL2 — — u = uninitialized bit; — = uni
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— © 2011 Microchip Technology Inc. Legend: Note 1: — — — — — — — — — — — — — Bit 4 — — — — SATDW ACCSAT Bit 5 YWM<3:0> SATB Bit 6 DISICNT<13:0> XB<14:0> SATA Bit 7 u = uninitialized bit; — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F5011/5013 4.0 Note: INTERRUPTS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The dsPIC30F Sensor and General Purpose Family has up to 41 interrupt sources and 4 processor exceptions (traps) which must be arbitrated based on a priority scheme.
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dsPIC30F5011/5013 4.1 Interrupt Priority The user-assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user. Note: The user-assignable priority levels start at 0 as the lowest priority and level 7 as the highest priority.
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dsPIC30F5011/5013 4.2 Reset Sequence A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The processor initializes its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory location immediately followed by the address target for the GOTO instruction.
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dsPIC30F5011/5013 Address Error Trap: 4.3.2 This trap is initiated when any of the following circumstances occurs: It is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the fixed priority shown in Figure 4-2 is implemented, which may require the user to check if other traps are pending, in order to completely correct the fault.
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dsPIC30F5011/5013 4.4 Interrupt Sequence 4.5 All interrupt event flags are sampled in the beginning of each instruction cycle by the IFSx registers. A pending interrupt request (IRQ) is indicated by the flag bit being equal to a ‘1’ in an IFSx register. The IRQ will cause an interrupt to occur if the corresponding bit in the Interrupt Enable (IECx) register is set. For the remainder of the instruction cycle, the priorities of all pending interrupt requests are evaluated.
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Bit 15 0086 0088 008C 008E 0090 0094 0096 0098 009A 009C 009E 00A0 00A2 00A4 00A6 IFS1 DS70116J-page 40 IFS2 IEC0 IEC1 IEC2 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 — Legend: Note 1: — — 00A8 INTTREG 00B0 C1IP<2:0> OC8IP<2:0> — — — — IC3IF — — — — IC3IE NVMIE INT2IP<2:0> IC6IP<2:0> — NVMIF OC3IP<2:0> CNIP<2:0> ADIP<2:0> T31P<2:0> T1IP<2:0> — IC4IE SI2CIE — IC4IF SI2CIF — Bit 12 — — — — — — — — — — — — C1IE ADIE
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dsPIC30F5011/5013 5.0 Note: ADDRESS GENERATOR UNITS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The dsPIC DSC core contains two independent address generator units: the X AGU and Y AGU.
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dsPIC30F5011/5013 5.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.
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dsPIC30F5011/5013 5.2.1 START AND END ADDRESS 5.2.2 The modulo addressing scheme requires that a starting and an ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-3). Note: Y space modulo addressing EA calculations assume word sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses.
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dsPIC30F5011/5013 5.2.3 MODULO ADDRESSING APPLICABILITY Modulo addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than, the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 5.
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dsPIC30F5011/5013 TABLE 5-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1
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dsPIC30F5011/5013 6.0 Note: FLASH PROGRAM MEMORY 6.2 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions.
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dsPIC30F5011/5013 6.4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary.
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dsPIC30F5011/5013 6.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 6.6.1 4. 5.
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dsPIC30F5011/5013 6.6.3 LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer.
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0766 NVMKEY — — WR Bit 15 — — WREN Bit 14 — — WRERR Bit 13 NVM REGISTER MAP(1) — — — — — — — — — Bit 12 Bit 11 Bit 10 — — — Bit 9 — Bit 7 — — NVMADR<15:0> TWRI Bit 8 Bit 6 u = uninitialized bit; — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0764 NVMADRU Legend: Note 1: 0760 0762 NVMADR Addr.
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dsPIC30F5011/5013 7.0 Note: DATA EEPROM MEMORY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Data EEPROM Memory is readable and writable during normal operation over the entire VDD range. The data EEPROM memory is directly mapped in the program memory address space.
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dsPIC30F5011/5013 7.2 7.2.1 Erasing Data EEPROM ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register. Setting the WR bit initiates the erase as shown in Example 7-2.
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dsPIC30F5011/5013 7.3 Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. 2. 3. Erase data EEPROM word. a) Select word, data EEPROM erase and set WREN bit in NVMCON register. b) Write address of word to be erased into NVMADR. c) Enable NVM interrupt (optional). d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit. This will begin erase cycle. g) Either poll NVMIF bit or wait for NVMIF interrupt.
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dsPIC30F5011/5013 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, and then set the NVMCON register and program the block. EXAMPLE 7-5: MOV MOV MOV MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV TBLWTL MOV MOV DISI MOV MOV MOV MOV BSET NOP NOP 7.
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dsPIC30F5011/5013 8.0 Note: I/O PORTS Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
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dsPIC30F5011/5013 FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Output Multiplexers Peripheral Module Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Output Enable 0 Peripheral Output Data 1 PIO Module Output Data 0 Read TRIS I/O Pad Data Bus D WR TRIS CK Q TRIS Latch D WR LAT + WR Port Q CK Data Latch Read LAT Input Data Read Port 8.
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DS70116J-page 60 LATD — — — — — Bit 14 — Bit 15 — — — Bit 13 — — — Bit 12 Bit 10 Bit 9 LATD11 RD11 LATD10 RD10 LATD9 RD9 TRISD11 TRISD10 TRISD9 Bit 11 PORTD REGISTER MAP FOR dsPIC30F5011(1) LATD14 LATD12 LATD11 RD11 LATD10 RD10 LATD9 RD9 LATD8 RD8 TRISD8 Bit 8 LATD7 RD7 TRISD7 Bit 7 — — — — 02E0 02E2 LATF — — — Bit 13 — — — Bit 12 — — — Bit 11 — — — Bit 10 — — — Bit 9 — — — Bit 8 — — — Bit 7 Bit 6 LATF6 RF6 Bit 4 Bit 3 Bit 2 Bi
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dsPIC30F5011/5013 8.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor, in response to a change of state on selected input pins. This module is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. There are up to 24 external signals (CN0 through CN23) that may be selected (enabled) for generating an interrupt request on a change of state.
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dsPIC30F5011/5013 9.0 Note: TIMER1 MODULE These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F5011/5013 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0). When the CPU goes into the Idle mode, the timer will stop incrementing unless TSIDL = 0.
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Bit 8 Bit 7 TON — TSIDL — — — — — Bit 6 — TGATE Period Register 1 Timer1 Register u = uninitialized bit; — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Bit 9 Legend: Note 1: Bit 10 0104 Bit 11 0102 Bit 12 T1CON Bit 13 PR1 Bit 14 0100 Bit 15 Addr.
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dsPIC30F5011/5013 10.0 Note: TIMER2/3 MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer.
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dsPIC30F5011/5013 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 16 Read TMR2 16 Reset ADC Event Trigger Equal TMR3 TMR2 MSB LSB Comparator x 32 PR3 T3IF Event Flag Sync PR2 0 1 D Q CK TGATE (T2CON<6>) TCS TGATE TGATE (T2CON<6>) Q T2CK Note: 1x Gate Sync 01 TCY 00 TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 Timer Configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation.
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dsPIC30F5011/5013 FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Reset T2IF Event Flag Comparator x 16 TMR2 Sync 0 1 Q D Q CK TGATE TCS TGATE TGATE T2CK FIGURE 10-3: 1x Gate Sync 01 TCY 00 TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal Reset T3IF Event Flag Comparator x 16 TMR3 0 1 Q D Q CK T3CK TCS TGATE TGATE TGATE Sync 1x 01 TCY © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 10.1 Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0).
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— — — — u = uninitialized bit; — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F5011/5013 11.0 Note: TIMER4/5 MODULE • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral modules, such as input capture and output compare This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F5011/5013 FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Reset TMR4 Sync 0 1 Q D Q CK TGATE TCS TGATE T4IF Event Flag Comparator x 16 TGATE T4CK FIGURE 11-3: 1x Gate Sync 01 TCY 00 TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 16-BIT TIMER5 BLOCK DIAGRAM PR5 ADC Event Trigger Equal Reset TMR5 0 1 Q D Q CK TGATE TCS TGATE T5IF Event Flag Comparator x 16 TGATE T5CK Sync 1x 01 TCY Note: TON TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 00 In the dsPIC30F5011 device, th
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0118 011A 011C 011E 0120 TMR5 PR4 PR5 T4CON T5CON TON TON Bit 15 — — Bit 14 TSIDL TSIDL Bit 13 — — Bit 12 — — Bit 11 TIMER4/5 REGISTER MAP(1) Bit 9 Bit 7 Bit 6 Timer 4 Register Bit 8 Bit 5 — — — — — — — — TGATE TGATE Period Register 5 Period Register 4 Timer 5 Register TCKPS1 TCKPS1 Timer 5 Holding Register (for 32-bit operations only) Bit 10 u = uninitialized bit; — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descrip
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dsPIC30F5011/5013 12.0 INPUT CAPTURE MODULE Note: 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F5011/5013 12.1.2 CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO. As each word is read from the FIFO, the remaining words are advanced by one position within the buffer.
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dsPIC30F5011/5013 13.0 Note: OUTPUT COMPARE MODULE The key operational features of the output compare module include: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). • • • • • • This section describes the output compare module and associated operational modes.
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dsPIC30F5011/5013 13.1 Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.
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dsPIC30F5011/5013 13.4.2 PWM PERIOD When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1.
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dsPIC30F5011/5013 13.5 Output Compare Operation During CPU Sleep Mode When the CPU enters Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state. For example, if the pin was high when the CPU entered the Sleep state, the pin will remain high. Likewise, if the pin was low when the CPU entered the Sleep state, the pin will remain low.
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0196 © 2011 Microchip Technology Inc. 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC 01AE — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F5011/5013 14.0 Note: SPI™ MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The Serial Peripheral Interface (SPI™) module is a synchronous serial interface.
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dsPIC30F5011/5013 FIGURE 14-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Receive Transmit SPIxSR SDIx bit 0 SDOx SSx Shift Clock Clock Control SS & FSYNC Control Edge Select Secondary Prescaler 1:1 – 1:8 SCKx Primary Prescaler 1, 4, 16, 64 FCY Enable Master Clock Note: x = 1 or 2.
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dsPIC30F5011/5013 14.3 Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven. Also, the SPI module is resynchronized, and all counters/control circuitry are reset.
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DS70116J-page 90 0228 022A SPI2CON SPI2BUF — — — SPIEN Bit 15 FRMEN — Bit 14 SPIFSD SPISIDL Bit 13 — — Bit 12 SPI2 REGISTER MAP(1) SPIFSD SPISIDL — FRMEN — — — Bit 10 DISSDO MODE16 — Bit 11 DISSDO MODE16 — — CKE — SSEN CKP SPIROV Bit 6 CKE — Bit 8 SSEN — Bit 7 Bit 6 CKP SPIROV Transmit and Receive Buffer SMP — Bit 9 Transmit and Receive Buffer SMP — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of
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dsPIC30F5011/5013 15.0 Note: I2C™ MODULE 15.1.1 This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F5011/5013 FIGURE 15-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV SCL Read Shift Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect I2CSTAT Write Control Logic Start, Restart, Stop bit Generate Write I2CCON Collision Detect Acknowledge Generation Clock Stretching Read Read Write I2CTRN LSB Shift Clock Read Reload Control BRG Down Counter DS70116J-page 92 Write I2CBRG FCY Read © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 15.2 I2C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received, it is compared to the 7 LSbs of the I2CADD register. If the A10M bit is ‘1’, the address is assumed to be a 10-bit address.
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dsPIC30F5011/5013 15.4.1 10-BIT MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 15.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated Start, Reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. 15.
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dsPIC30F5011/5013 15.7 Interrupts The I2C module generates two interrupt flags, MI2CIF (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Interrupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. 15.8 Slope Control The I2C standard requires slope control on the SDA and SCL signals for Fast mode (400 kHz).
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dsPIC30F5011/5013 15.12.3 BAUD RATE GENERATOR 2 In I C Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbitration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high. As per the I2C standard, FSCK may be 100 kHz or 400 kHz. However, the user can specify any baud rate up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
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— — — — — — — I2CSIDL SCLREL IPMIEN — — — — BCL A10M — — — Bit 10 GCSTAT DISSLW — — — Bit 9 ADD10 SMEN — — Bit 8 IWCOL GCEN Bit 7 — = unimplemented, read as ‘0’ Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F5011/5013 16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE Note: 16.1 The key features of the UART module are: • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F5011/5013 FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Write Read Read Read UxMODE Write UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Load RSR to Buffer Receive Shift Register (UxRSR) Control Signals FERR UxRX 8-9 PERR LPBACK From UxTX 1 16 Divider 16x Baud Clock from Baud Rate Generator UxRXIF DS70116J-pag
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dsPIC30F5011/5013 16.2 16.2.1 Enabling and Setting Up UART ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input respectively, overriding the TRIS and LATCH register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘1’ when no transmission is taking place. 16.2.2 16.3 16.3.1 Disabling the UART module resets the buffers to empty states.
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dsPIC30F5011/5013 16.3.4 TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit: a) b) If UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty word.
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dsPIC30F5011/5013 16.5.2 FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’, otherwise FERR will be set. The read-only FERR bit is buffered along with the received data. It is cleared on any Reset. 16.5.3 PARITY ERROR (PERR) The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected.
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dsPIC30F5011/5013 16.9 Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. 16.10.
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© 2011 Microchip Technology Inc. — U2STA — — — — — — UTX8 LPBACK Bit 6 Baud Rate Generator Prescaler URX8 u = uninitialized bit; — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F5011/5013 17.0 Note: 17.1 CAN MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). Overview The Controller Area Network (CAN) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices.
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dsPIC30F5011/5013 FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 BUFFERS Acceptance Filter RXF2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB2 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF MESSAGE TXB1 MSGREQ TXABT TXLARB TXERR MTXBUFF TXB0 A c c e p t R X B 0 Message Queue Control Transmit Byte Sequencer Acceptance Mask RXM0 Acceptance Filter RXF3 Acceptance Filter RXF0 Acceptance Filter RXF4 Acceptance Filter RXF1 Acceptance Filter RXF5 Identifier M A B
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dsPIC30F5011/5013 17.3 Modes of Operation The CAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Loopback Mode Error Recognition Mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>).
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dsPIC30F5011/5013 17.4 17.4.1 Message Reception RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). There are 2 receive buffers visible, RXB0 and RXB1, that can essentially instantaneously receive a complete message from the protocol engine.
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dsPIC30F5011/5013 • Receive Error Interrupts: A receive error interrupt will be indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt Status register, CiINTF. - Invalid Message Received: If any type of error occurred during reception of the last message, an error will be indicated by the IVRIF bit. - Receiver Overrun: The RXnOVR bit indicates that an overrun condition occurred.
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dsPIC30F5011/5013 17.5.6 17.6 TRANSMIT INTERRUPTS Baud Rate Setting Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: All nodes on any particular CAN bus must have the same nominal bit rate. In order to set the baud rate, the following parameters have to be initialized: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
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dsPIC30F5011/5013 17.6.2 PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64, in addition to a fixed divide-by-2 for clock generation. The time quantum (TQ) is a fixed unit of time derived from the oscillator period, and is given by Equation 17-1, where FCAN is FCY (if the CANCKS bit is set) or 4FCY (if CANCKS is clear). Note: FCAN must not exceed 30 MHz. If CANCKS = 0, then FCY must not exceed 7.5 MHz.
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DS70116J-page 114 — — — — 0318 C1RXF3SID C1RXF3EIDH 031A — — — — 0328 C1RXF5SID C1RXF5EIDH 032A — — — — — — 0338 — — — — — — — — — — — — 0346 0348 034A 034C 034E 0350 0352 0354 0356 C1TX2B1 C1TX2B2 C1TX2B3 C1TX2B4 C1TX2CON C1TX1SID C1TX1EID C1TX1DLC C1TX1B1 Legend: Note 1: 0344 C1TX2DLC — — — — Bit 6 Bit 5 — — — — — — — — — — — — — — — — — — — — TXRTR — — — TXRTR — — — — — — — — — — — — — — — — — — — — TXRB1 —
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dsPIC30F5011/5013 18.0 Note: 18.1 DATA CONVERTER INTERFACE (DCI) MODULE This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046).
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dsPIC30F5011/5013 FIGURE 18-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate CSCK Generator FSD Word Size Selection bits 16-bit Data Bus Frame Length Selection bits DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO DS70116J-page 118 © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 18.3 18.3.1 DCI Module Operation MODULE ENABLE The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Clearing the DCIEN control bit has the effect of resetting the module. In particular, all counters associated with CSCK generation, frame sync and the DCI buffer control unit are Reset. The DCI clocks are shutdown when the DCIEN bit is cleared. When enabled, the DCI controls the data direction for the four I/O pins associated with the module.
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dsPIC30F5011/5013 In the Multi-Channel mode, a new data frame transfer will begin one CSCK cycle after the COFS pin is sampled high (see Figure 18-2). The pulse on the COFS pin resets the frame sync generator logic. In the I2S mode, a new data word will be transferred one CSCK cycle after a low-to-high or a high-to-low transition is sampled on the COFS pin. A rising or falling edge on the COFS pin resets the frame sync generator logic.
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dsPIC30F5011/5013 18.3.7 BIT CLOCK GENERATOR EQUATION 18-2: The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock will be disabled. If the BCG<11:0> bits are set to a nonzero value, the bit clock generator is enabled.
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dsPIC30F5011/5013 18.3.8 SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sampled on the falling edge of the CSCK signal. If the CSCK bit is set, data will be sampled on the rising edge of CSCK.
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dsPIC30F5011/5013 18.3.14 BUFFER LENGTH CONTROL The amount of data that is buffered between interrupts is determined by the buffer length (BLEN<1:0>) control bits in the DCICON1 SFR. The size of the transmit and receive buffers may be varied from 1 to 4 data words using the BLEN control bits. The BLEN control bits are compared to the current value of the DCI buffer control unit address counter.
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dsPIC30F5011/5013 18.3.18 SLOT STATUS BITS The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers. 18.3.
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dsPIC30F5011/5013 18.6.2 20-BIT AC-LINK MODE The 20-bit AC-Link mode allows all bits in the data time slots to be transmitted and received but does not maintain data alignment in the TXBUF and RXBUF registers. The 20-bit AC-Link mode functions similar to the MultiChannel mode of the DCI module, except for the duty cycle of the frame synchronization signal. The AC-Link frame synchronization signal should remain high for 16 CSCK cycles and should be low for the following 240 cycles.
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0242 0244 DCICON3 DS70116J-page 126 025A 025C 025E — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F5011/5013 19.0 Note: 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC module has six 16-bit registers: • • • • • • This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). The ADCON1, ADCON2 and ADCON3 registers control the operation of the ADC module.
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dsPIC30F5011/5013 19.1 ADC Result Buffer The ADC module contains a 16-word, dual port, readonly buffer called ADCBUF0...ADCBUFF, to buffer the ADC results. The RAM is 12 bits wide, but the data obtained is represented in one of four different 16-bit data formats. The contents of the sixteen ADC Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software. 19.
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dsPIC30F5011/5013 19.4 Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to four alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control. Clearing the SAMP bit will cause the conversion trigger.
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dsPIC30F5011/5013 19.7 ADC Speeds The dsPIC30F 12-bit ADC specifications permit a maximum of 200 ksps sampling rate. The table below summarizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-bit ADC Conversion Rates Speed Up to 200 ksps(1) TAD Sampling Minimum Time Min 334 ns 1 TAD Rs Max VDD Temperature 2.5 kΩ 4.5V to 5.
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dsPIC30F5011/5013 Figure 19-2 depicts the recommended circuit for the conversion rates above 100 ksps. The dsPIC30F5013 is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 63 62 61 65 64 VSS 69 68 67 66 1 60 2 59 3 4 58 5 6 56 7 54 8 9 53 57 52 C2 0.1 μF 49 R1 10 C7 0.1 μF VDD C6 0.01 μF VDD AVDD C5 1 μF AVDD C4 0.1 μF AVDD C3 0.
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dsPIC30F5011/5013 FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 TAD SAMPLING TIME TSAMP = 1 TAD TSAMP = 1 TAD ADCLK TCONV = 14 TAD TCONV = 14 TAD SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 ADC Acquisition Requirements The analog input model of the 12-bit ADC is shown in Figure 19-4. The total sampling time for the ADC is a function of the internal amplifier settling time and the holding capacitor charge time.
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dsPIC30F5011/5013 19.9 Module Power-down Modes The module has two internal Power modes. When the ADON bit is ‘1’, the module is in Active mode, and is fully powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the circuit are disabled for maximum current savings. In order to return to the Active mode from Off mode, the user must wait for the ADC circuitry to stabilize. 19.10 ADC Operation During CPU Sleep and Idle Modes 19.10.
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dsPIC30F5011/5013 FIGURE 19-5: ADC OUTPUT DATA FORMATS RAM Contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Signed Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 Signed Integer Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 19.13 Configuring Analog Port Pins 19.
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dsPIC30F5011/5013 20.0 Note: SYSTEM INTEGRATION This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F5011/5013 TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2. XT 4 MHz-10 MHz crystal on OSC1:OSC2. XT w/ PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/ PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/ PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled(1). LP 32 kHz crystal on SOSCO:SOSCI(2). HS 10 MHz-25 MHz crystal. EC External clock input (0-40 MHz).
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dsPIC30F5011/5013 FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 OSC2 Primary Oscillator PLL x4, x8, x16 PLL Lock COSC<1:0> Primary Osc TUN<3:0> 4 NOSC<1:0> Primary Oscillator Stability Detector OSWEN Internal Fast RC Oscillator (FRC) POR Done Oscillator Start-up Timer Clock Secondary Osc Switching and Control Block SOSCO SOSCI 32 kHz LP Oscillator Secondary Oscillator Stability Detector Internal LowPower RC Oscilla
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dsPIC30F5011/5013 20.2 20.2.1 Oscillator Configurations INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: • FOS<1:0> Configuration bits, which select one of four oscillator groups, and • FPR<3:0> Configuration bits, which select one of 13 oscillator choices within the primary group Table 20-2 shows the Configuration bit values for clock selection.
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dsPIC30F5011/5013 20.2.4 PHASE LOCKED LOOP (PLL) The PLL multiplies the clock which is generated by the primary oscillator or Fast RC oscillator. The PLL is selectable to have gains of x4, x8, and x16. Input and output frequency ranges are summarized in Table 20-3. TABLE 20-3: PLL FREQUENCY RANGE FIN PLL Multiplier FOUT 4 MHz-10 MHz x4 16 MHz-40 MHz 4 MHz-10 MHz x8 32 MHz-80 MHz 4 MHz-7.
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dsPIC30F5011/5013 20.2.7 FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, the LPRC internal oscillator will run at all times (except during Sleep mode) and is not subject to control by the SWDTEN bit.
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dsPIC30F5011/5013 20.3 Reset 20.3.
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dsPIC30F5011/5013 FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 20-4: VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset DS70116J-page 144 © 2011 Microchip Technology
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dsPIC30F5011/5013 20.3.1.1 POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time.
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dsPIC30F5011/5013 Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column.
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dsPIC30F5011/5013 20.4 20.4.1 Watchdog Timer (WDT) WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free-running timer which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the crystal oscillator) fails. 20.4.
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dsPIC30F5011/5013 Any interrupt that is individually enabled (using the corresponding IE bit), and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The Sleep Status bit in the RCON register is set upon wake-up. Note: In spite of various delays applied (TPOR, TLOCK and TPWRT), the crystal oscillator (and PLL) may not be active at the end of the time-out (e.g., for low frequency crystals).
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dsPIC30F5011/5013 20.8 Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral will also be disabled so writes to those registers will have no effect and read values will be invalid.
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DS70116J-page 150 PMD2 IC8MD T5MD TUN3 IC7MD T4MD TUN2 Bit 13 IC6MD T3MD IC5MD T2MD COSC<1:0> LVDEN Bit 12 IC4MD T1MD TUN1 Bit 11 Bit 9 IC3MD — TUN0 Bit 8 IC2MD — IC1MD DCIMD NOSC<1:0> LVDL<3:0> Bit 10 SWR Bit 6 U2MD OC8MD OC7MD I2CMD POST<1:0> EXTR Bit 7 — BKBUG COE — — — — — — — — — — ESS<1:0> — = unimplemented, read as ‘0’ Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
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dsPIC30F5011/5013 21.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).
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dsPIC30F5011/5013 All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 Most Significant bits are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP.
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dsPIC30F5011/5013 TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register ∈ {W0..
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dsPIC30F5011/5013 TABLE 21-2: Base Instr # 1 2 3 4 5 6 7 8 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW DS70116J-page 154 Assembly Syntax Description # of # of Words Cycles Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + li
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dsPIC30F5011/5013 TABLE 21-2: Base Instr # 9 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTG BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 BTG Ws,#bit4 Bit Toggle Ws 1 1 None None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit
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dsPIC30F5011/5013 TABLE 21-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax Description # of # of Words Cycles Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
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dsPIC30F5011/5013 TABLE 21-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY.N MPY.N MSC MSC 51 MUL 53 54 NOP POP Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, AWB MUL.
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dsPIC30F5011/5013 TABLE 21-2: Base Instr # 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic SAC Assembly Syntax Description # of # of Words Cycles Status Flags Affected SAC Acc,#Slit4,Wdo Store Accumulator 1 1 SAC.
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dsPIC30F5011/5013 22.
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dsPIC30F5011/5013 22.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 22.
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dsPIC30F5011/5013 22.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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dsPIC30F5011/5013 22.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 22.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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dsPIC30F5011/5013 23.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to the ”dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below.
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dsPIC30F5011/5013 23.1 DC Characteristics TABLE 23-1: OPERATING MIPS VS. VOLTAGE VDD Range Temp Range 4.75-5.5V -40°C to 85°C 4.75-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C TABLE 23-2: Max MIPS dsPIC30F501X-30I dsPIC30F501X-20I dsPIC30F501X-20E 30 20 — — — 20 15 10 — — — 10 7.5 7.
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dsPIC30F5011/5013 TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units 2.5 — 5.5 V Industrial temperature 3.0 — 5.
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dsPIC30F5011/5013 TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC23a 13.5 20 mA 25°C DC23b 14 21 mA 85°C DC23c 15 22.5 mA 125°C DC23e 23 34.5 mA 25°C DC23f 23.
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dsPIC30F5011/5013 TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1,2) Max Units Conditions Idle Current (IIDLE): Core OFF Clock ON Base Current(2) DC50a 4.8 7.2 mA 25°C DC50b 4.9 7.3 mA 85°C DC50c 5.0 7.5 mA 125°C DC50e 8.9 13.3 mA 25°C DC50f 8.8 13.2 mA 85°C DC50g 8.8 13.
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dsPIC30F5011/5013 TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units 25 μA Conditions Power Down Current (IPD)(2) DC60a 5 25°C DC60b 8 40 μA 85°C DC60c 14 70 μA 125°C DC60e 8 40 μA 25°C DC60f 12 55 μA 85°C DC60g 20 100 μA 125°C DC61a 7.
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dsPIC30F5011/5013 TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.
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dsPIC30F5011/5013 TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units — 0.6 V Conditions Output Low Voltage(2) VOL DO10 I/O ports — IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKOUT — — 0.6 V IOL = 1.
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dsPIC30F5011/5013 TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. BO10 Symbol VBOR Characteristic BOR Voltage(2) on VDD transition high to low BORV = 11(3) Min Typ(1) Max Units — — — V BORV = 10 2.60 — 2.71 V BORV = 01 4.10 — 4.40 V BORV = 00 4.58 — 4.
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dsPIC30F5011/5013 23.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Operating voltage VDD range as described in Table 23-1.
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dsPIC30F5011/5013 TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic Min Typ(1) Max Units External CLKIN Frequency(2) (External clocks allowed only in EC mode) DC 4 4 4 — — — — 40 10 10 7.5 MHz MHz MHz MHz EC EC with 4x PLL EC with 8x PLL EC with 16x PLL Oscillator Frequency(2) DC 0.
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dsPIC30F5011/5013 TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 TABLE 23-17: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator Mode FOSC (MHz)(1) TCY (μsec)(2) MIPS(3) w/o PLL EC 0.200 20.0 0.05 — — — 4 1.0 1.0 4.0 8.0 16.0 XT Note 1: 2: 3: MIPS(3) w PLL x4 MIPS(3) w PLL x8 MIPS(3) w PLL x16 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Assumption: Oscillator Postscaler is divide by 1. Instruction Execution Cycle Time: TCY = 1 / MIPS.
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dsPIC30F5011/5013 FIGURE 23-5: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 23-3 for load conditions. TABLE 23-20: CLKOUT AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 FIGURE 23-6: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out OSC Time-out SY11 SY30 Internal RESET Watchdog Timer RESET SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. DS70116J-page 178 © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F5011/5013 FIGURE 23-7: BAND GAP START-UP TIME CHARACTERISTICS VBGAP 0V Enable Band Gap (see Note) Band Gap Stable SY40 Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set. TABLE 23-22: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param No. SY40 Note 1: 2: Symbol TBGAP Standard Operating Conditions: 2.5V to 5.
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dsPIC30F5011/5013 FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRX Note: Refer to Figure 23-3 for load conditions. TABLE 23-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 TABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 Symbol TtxH TtxL TtxP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Conditions Synchronous, no prescaler 0.
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dsPIC30F5011/5013 FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure 23-3 for load conditions. TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 FIGURE 23-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC10 OC11 Note: Refer to Figure 23-3 for load conditions. TABLE 23-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 2.5V to 5.
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dsPIC30F5011/5013 FIGURE 23-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F5011/5013 FIGURE 23-12: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO HIGH-Z 70 CS50 LSb MSb CS30 CSDI MSb IN HIGH-Z CS31 LSb IN CS40 CS41 Note: Refer to Figure 23-3 for load conditions. DS70116J-page 186 © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 TABLE 23-29: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS75 CS76 CS80 SDO (CSDO) MSb LSb LSb CS76 CS75 MSb IN SDI (CSDI) CS65 CS66 TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 FIGURE 23-14: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx BIT14 - - - - - -1 SP31 SDIx MSb IN LSb SP30 LSb IN BIT14 - - - -1 SP40 SP41 Note: Refer to Figure 23-3 for load conditions. TABLE 23-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F5011/5013 FIGURE 23-15: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 BIT14 - - - - - -1 MSb SDOX SP40 SDIX LSb SP30,SP31 MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure 23-3 for load conditions. TABLE 23-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F5011/5013 FIGURE 23-16: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX BIT14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.
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dsPIC30F5011/5013 FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP52 MSb SDOX BIT14 - - - - - -1 LSb SP30,SP31 SDIX MSb IN BIT14 - - - -1 SP51 LSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. DS70116J-page 192 © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 FIGURE 23-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Stop Condition Start Condition Note: Refer to Figure 23-3 for load conditions. FIGURE 23-19: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure 23-3 for load conditions. DS70116J-page 194 © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 TABLE 23-35: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
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dsPIC30F5011/5013 FIGURE 23-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS34 IS31 IS30 IS33 SDA Stop Condition Start Condition FIGURE 23-21: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out DS70116J-page 196 © 2011 Microchip Technology Inc.
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dsPIC30F5011/5013 TABLE 23-36: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC30F5011/5013 FIGURE 23-22: CXTX Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CXRX Pin (input) CA20 TABLE 23-37: CAN MODULE I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 2.5V to 5.
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dsPIC30F5011/5013 TABLE 23-38: 12-BIT A/D MODULE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply Greater of VDD - 0.3 or 2.7 — Lesser of VDD + 0.3 or 5.5 V VSS - 0.3 — VSS + 0.
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dsPIC30F5011/5013 TABLE 23-38: 12-BIT A/D MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. AD24 Symbol Characteristic Min. Typ Max. Units Conditions EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD24A EOFF Offset Error -2 -1.5 -1.
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dsPIC30F5011/5013 FIGURE 23-23: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 DONE ADIF ADRES(0) 1 2 3 4 5 6 7 8 9 1 – Software sets ADCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 18. “12-bit A/D Converter” (DS70046) of the “dsPIC30F Family Reference Manual”. 3 – Software clears ADCON.
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dsPIC30F5011/5013 TABLE 23-39: 12-BIT A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions VDD = 3-5.5V (Note 1) Clock Parameters AD50 TAD A/D Clock Period — 334 — ns AD51 TRC A/D Internal RC Oscillator Period 1.2 1.5 1.
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dsPIC30F5011/5013 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC 30F5011 -30I/PT e3 07160S1 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
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dsPIC30F5011/5013 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 64 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
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dsPIC30F5011/5013 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 80 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
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dsPIC30F5011/5013 APPENDIX A: REVISION HISTORY Revision F (May 2006) Previous versions of this data sheet contained Advance or Preliminary Information. They were distributed with incomplete characterization data. Revision F of this document reflects the following updates: • Supported I2C Slave Addresses (see Table 15-1) • ADC Conversion Clock selection to allow 200 kHz sampling rate (see Section 19.
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dsPIC30F5011/5013 Revision J (January 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Section 20.0 “System Integration” Added a shaded note on OSCTUN functionality in Section 20.2.5 “Fast RC Oscillator (FRC)”. Section 23.
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dsPIC30F5011/5013 INDEX Numerics 12-bit Analog-to-Digital Converter (A/D) Module .............. 127 A A/D .................................................................................... 127 Aborting a Conversion .............................................. 129 ADCHS Register ....................................................... 127 ADCON1 Register..................................................... 127 ADCON2 Register..................................................... 127 ADCON3 Register.......
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dsPIC30F5011/5013 Overflow and Saturation ............................................. 20 Round Logic ................................................................ 21 Write Back................................................................... 21 Data Address Space ........................................................... 28 Alignment .................................................................... 30 Alignment (Figure) ......................................................
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dsPIC30F5011/5013 I2C 10-bit Slave Mode Operation ........................................ 93 Reception.................................................................... 94 Transmission............................................................... 94 I2C 7-bit Slave Mode Operation .......................................... 93 Reception.................................................................... 93 Transmission...............................................................
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dsPIC30F5011/5013 Output Compare Sleep Mode Operation............................. 84 P Packaging Information ...................................................... 203 Marking ..................................................................... 203 Peripheral Module Disable (PMD) Registers .................... 149 Pinout Descriptions ............................................................. 12 PLL Clock Timing Specifications....................................... 175 POR. See Power-on Reset.
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dsPIC30F5011/5013 16-bit Asynchronous Counter Mode ........................... 63 16-bit Synchronous Counter Mode ............................. 63 16-bit Timer Mode....................................................... 63 Gate Operation ........................................................... 64 Interrupt....................................................................... 64 Operation During Sleep Mode .................................... 64 Prescaler..................................................
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dsPIC30F5011/5013 Unit ID Locations............................................................... 137 Universal Asynchronous Receiver Transmitter (UART) Module ............................................................................... 99 W Wake-up from Sleep ......................................................... 137 Wake-up from Sleep and Idle.............................................. 39 Watchdog Timer Timing Characteristics ..............................................
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dsPIC30F5011/5013 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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dsPIC30F5011/5013 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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dsPIC30F5011/5013 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.