Datasheet

© 2011 Microchip Technology Inc. DS70116J-page 215
dsPIC30F5011/5013
16-bit Asynchronous Counter Mode ........................... 63
16-bit Synchronous Counter Mode ............................. 63
16-bit Timer Mode....................................................... 63
Gate Operation ........................................................... 64
Interrupt....................................................................... 64
Operation During Sleep Mode .................................... 64
Prescaler..................................................................... 64
Real-Time Clock ......................................................... 64
Interrupts............................................................. 64
Oscillator Operation ............................................ 64
Register Map............................................................... 65
Timer2 and Timer3 Selection Mode .................................... 82
Timer2/3 Module ................................................................. 67
16-bit Timer Mode....................................................... 67
32-bit Synchronous Counter Mode ............................. 67
32-bit Timer Mode....................................................... 67
ADC Event Trigger...................................................... 70
Gate Operation ........................................................... 70
Interrupt....................................................................... 70
Operation During Sleep Mode .................................... 70
Register Map............................................................... 71
Timer Prescaler........................................................... 70
Timer4/5 Module ................................................................. 73
Register Map............................................................... 75
Timing Characteristics
A/D Conversion
Low-speed (ASAM = 0, SSRC = 000) .............. 201
Bandgap Start-up Time............................................. 180
CAN Module I/O........................................................ 198
CLKOUT and I/O....................................................... 177
DCI Module
AC-Link Mode ................................................... 188
Multichannel, I
2
S Modes................................... 186
External Clock........................................................... 173
I
2
C Bus Data
Master Mode..................................................... 194
Slave Mode....................................................... 196
I
2
C Bus Start/Stop Bits
Master Mode..................................................... 194
Slave Mode....................................................... 196
Input Capture (CAPX) ............................................... 183
OC/PWM Module ...................................................... 185
Oscillator Start-up Timer ........................................... 178
Output Compare Module........................................... 184
Power-up Timer ........................................................ 178
Reset......................................................................... 178
SPI Module
Master Mode (CKE = 0) .................................... 189
Master Mode (CKE = 1) .................................... 190
Slave Mode (CKE = 0) ...................................... 191
Slave Mode (CKE = 1) ...................................... 192
Type A, B and C Timer External Clock ..................... 181
Watchdog Timer........................................................ 178
Timing Diagrams
CAN Bit ..................................................................... 112
Frame Sync, AC-Link Start of Frame........................ 120
Frame Sync, Multi-Channel Mode ............................ 120
I
2
S Interface Frame Sync.......................................... 120
PWM Output ............................................................... 83
Time-out Sequence on Power-up (MCLR
Not Tied to
V
DD), Case 1..................................................... 144
Time-out Sequence on Power-up (MCLR
Not Tied to
V
DD), Case 2..................................................... 144
Time-out Sequence on Power-up (MCLR
Tied to VDD)..
144
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy .............. 175
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
Low-speed ........................................................ 202
Bandgap Start-up Time ............................................ 180
Brown-out Reset....................................................... 179
CAN Module I/O ....................................................... 198
CLKOUT and I/O ...................................................... 177
DCI Module
AC-Link Mode................................................... 188
Multichannel, I
2
S Modes................................... 187
External Clock .......................................................... 174
I
2
C Bus Data (Master Mode) .................................... 195
I
2
C Bus Data (Slave Mode) ...................................... 197
Input Capture............................................................ 183
Oscillator Start-up Timer........................................... 179
Output Compare Module .......................................... 184
Power-up Timer ........................................................ 179
Reset ........................................................................ 179
Simple OC/PWM Mode ............................................ 185
SPI Module
Master Mode (CKE = 0).................................... 189
Master Mode (CKE = 1).................................... 190
Slave Mode (CKE = 0)...................................... 191
Slave Mode (CKE = 1)...................................... 193
Type A Timer External Clock.................................... 181
Type B Timer External Clock.................................... 182
Type C Timer External Clock.................................... 182
Watchdog Timer ....................................................... 179
Timing Specifications
PLL Clock ................................................................. 175
PLL Jitter .................................................................. 175
Trap Vectors ....................................................................... 38
U
UART Module
Address Detect Mode ............................................... 103
Auto Baud Support ................................................... 104
Baud Rate Generator ............................................... 103
Enabling and Setting Up........................................... 101
Framing Error (FERR) .............................................. 103
Idle Status................................................................. 103
Loopback Mode ........................................................ 103
Operation During CPU Sleep and Idle Modes.......... 104
Overview..................................................................... 99
Parity Error (PERR) .................................................. 103
Receive Break .......................................................... 103
Receive Buffer (UxRXB)........................................... 102
Receive Buffer Overrun Error (OERR Bit) ................ 102
Receive Interrupt ...................................................... 102
Receiving Data ......................................................... 102
Receiving in 8-bit or 9-bit Data Mode ....................... 102
Reception Error Handling ......................................... 102
Transmit Break ......................................................... 102
Transmit Buffer (UxTXB) .......................................... 101
Transmit Interrupt ..................................................... 102
Transmitting Data ..................................................... 101
Transmitting in 8-bit Data Mode ............................... 101
Transmitting in 9-bit Data Mode ............................... 101
UART1 Register Map ............................................... 105
UART2 Register Map ............................................... 105
UART Operation
Idle Mode.................................................................. 104
Sleep Mode .............................................................. 104