Datasheet

© 2011 Microchip Technology Inc. DS70116J-page 213
dsPIC30F5011/5013
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2
C 10-bit Slave Mode Operation ........................................ 93
Reception.................................................................... 94
Transmission............................................................... 94
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2
C 7-bit Slave Mode Operation .......................................... 93
Reception.................................................................... 93
Transmission............................................................... 93
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2
C Master Mode Operation ................................................ 95
Baud Rate Generator.................................................. 96
Clock Arbitration.......................................................... 96
Multi-Master Communication, Bus Collision and Bus Ar-
bitration ............................................................... 96
Reception.................................................................... 95
Transmission............................................................... 95
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2
C Master Mode Support ................................................... 95
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2
C Module .......................................................................... 91
Addresses ................................................................... 93
Bus Data Timing Characteristics
Master Mode..................................................... 194
Slave Mode....................................................... 196
Bus Data Timing Requirements
Master Mode..................................................... 195
Slave Mode....................................................... 197
Bus Start/Stop Bits Timing Characteristics
Master Mode..................................................... 194
Slave Mode....................................................... 196
General Call Address Support .................................... 95
Interrupts..................................................................... 95
IPMI Support ............................................................... 95
Operating Function Description .................................. 91
Operation During CPU Sleep and Idle Modes ............ 96
Pin Configuration ........................................................ 91
Programmer’s Model................................................... 91
Register Map............................................................... 97
Registers..................................................................... 91
Slope Control .............................................................. 95
Software Controlled Clock Stretching (STREN = 1).... 94
Various Modes ............................................................ 91
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2
S Mode Operation .......................................................... 125
Data Justification....................................................... 125
Frame and Data Word Length Selection................... 125
Idle Current (I
IDLE) ............................................................ 167
In-Circuit Serial Programming (ICSP) ......................... 47, 137
Input Capture (CAPX) Timing Characteristics .................. 183
Input Capture Module ......................................................... 77
Interrupts..................................................................... 78
Register Map............................................................... 79
Input Capture Operation During Sleep and Idle Modes ...... 78
CPU Idle Mode............................................................ 78
CPU Sleep Mode ........................................................ 78
Input Capture Timing Requirements ................................. 183
Input Change Notification Module....................................... 62
dsPIC30F5011 Register Map (Bits 15-8) .................... 62
dsPIC30F5011 Register Map (Bits 7-0) ...................... 62
dsPIC30F5013 Register Map (Bits 15-8) .................... 62
dsPIC30F5013 Register Map (Bits 7-0) ...................... 62
Instruction Addressing Modes............................................. 41
File Register Instructions ............................................ 41
Fundamental Modes Supported.................................. 41
MAC Instructions......................................................... 42
MCU Instructions ........................................................ 41
Move and Accumulator Instructions............................ 42
Other Instructions........................................................ 42
Instruction Set
Overview ................................................................... 154
Summary................................................................... 151
Internal Clock Timing Examples ....................................... 175
Internet Address ............................................................... 215
Interrupt Controller
Register Map .............................................................. 40
Interrupt Priority .................................................................. 36
Traps .......................................................................... 37
Interrupt Sequence ............................................................. 39
Interrupt Stack Frame................................................. 39
Interrupts ............................................................................ 35
L
Load Conditions................................................................ 173
Low Voltage Detect (LVD) ................................................ 147
Low-Voltage Detect Characteristics.................................. 170
LVDL Characteristics ........................................................ 171
M
Memory Organization ......................................................... 23
Core Register Map ..................................................... 32
Microchip Internet Web Site.............................................. 215
Modes of Operation
Disable...................................................................... 109
Initialization............................................................... 109
Listen All Messages.................................................. 109
Listen Only................................................................ 109
Loopback .................................................................. 109
Normal Operation ..................................................... 109
Modulo Addressing............................................................. 42
Applicability................................................................. 44
Incrementing Buffer Operation Example .................... 43
Start and End Address ............................................... 43
W Address Register Selection.................................... 43
MPLAB ASM30 Assembler, Linker, Librarian................... 160
MPLAB Integrated Development Environment Software.. 159
MPLAB PM3 Device Programmer .................................... 162
MPLAB REAL ICE In-Circuit Emulator System ................ 161
MPLINK Object Linker/MPLIB Object Librarian ................ 160
N
NVM
Register Map .............................................................. 51
O
OC/PWM Module Timing Characteristics ......................... 185
Operating Current (I
DD) .................................................... 165
Oscillator
Configurations .......................................................... 140
Fail-Safe Clock Monitor .................................... 142
Fast RC (FRC).................................................. 141
Initial Clock Source Selection ........................... 140
Low Power RC (LPRC)..................................... 141
LP Oscillator Control......................................... 140
Phase Locked Loop (PLL) ................................ 141
Start-up Timer (OST)........................................ 140
Operating Modes (Table).......................................... 138
System Overview...................................................... 137
Oscillator Selection........................................................... 137
Oscillator Start-up Timer
Timing Characteristics .............................................. 178
Timing Requirements ............................................... 179
Output Compare Interrupts ................................................. 84
Output Compare Module .................................................... 81
Register Map .............................................................. 85
Timing Characteristics .............................................. 184
Timing Requirements ............................................... 184
Output Compare Operation During CPU Idle Mode ........... 84