Datasheet

 2010 Microchip Technology Inc. DS70138G-page 223
dsPIC30F3014/4013
CAN Module I/O........................................................205
CLKOUT and I/O.......................................................185
DCI Module
AC-Link Mode ................................................... 194
Multichannel, I
2
S Modes................................... 192
External Clock........................................................... 181
Frame Sync, AC-Link Start-Of-Frame....................... 124
Frame Sync, Multichannel Mode ..............................124
I
2
C Bus Data
Master Mode.....................................................201
Slave Mode.......................................................203
I
2
C Bus Start/Stop Bits
Master Mode.....................................................201
Slave Mode.......................................................203
I
2
S Interface Frame Sync.......................................... 124
Input Capture (CAPx)................................................ 190
Low-Voltage Detect................................................... 178
OCx/PWM Module ....................................................191
Oscillator Start-up Timer...........................................186
Output Compare Module........................................... 190
Power-up Timer ........................................................186
PWM Output ...............................................................87
Reset.........................................................................186
SPI Module
Master Mode (CKE = 0)....................................195
Master Mode (CKE = 1)....................................196
Slave Mode (CKE = 0)......................................197
Slave Mode (CKE = 1)......................................199
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1...................... 152
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2...................... 152
Time-out Sequence on Power-up
(MCLR
Tied to VDD)..........................................152
Type A, B and C Timer External Clock ..................... 188
Watchdog Timer........................................................ 186
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy...............183
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
Low-Speed........................................................ 209
Band Gap Start-up Time........................................... 187
Brown-out Reset ....................................................... 187
CAN Module I/O........................................................205
CLKOUT and I/O.......................................................185
DCI Module
AC-Link Mode ................................................... 195
Multichannel, I
2
S Modes................................... 193
External Clock........................................................... 182
I
2
C Bus Data (Master Mode)..................................... 201
I
2
C Bus Data (Slave Mode)....................................... 204
Input Capture ............................................................ 190
Oscillator Start-up Timer...........................................187
Output Compare Module........................................... 190
Power-up Timer ........................................................187
Reset.........................................................................187
Simple OCx/PWM Mode...........................................191
SPI Module
Master Mode (CKE = 0)....................................196
Master Mode (CKE = 1)....................................197
Slave Mode (CKE = 0)......................................198
Slave Mode (CKE = 1)......................................200
Type A Timer External Clock ....................................188
Type B Timer External Clock ....................................189
Type C Timer External Clock.................................... 189
Watchdog Timer ....................................................... 187
Trap Vectors....................................................................... 63
U
UART Module
Address Detect Mode ............................................... 107
Auto-Baud Support ................................................... 108
Baud Rate Generator ............................................... 107
Enabling and Setting Up........................................... 105
Framing Error (FERR) .............................................. 107
Idle Status................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes.......... 108
Overview................................................................... 103
Parity Error (PERR).................................................. 107
Receive Break .......................................................... 107
Receive Buffer (UxRXB)........................................... 106
Receive Buffer Overrun Error (OERR Bit)................ 106
Receive Interrupt ...................................................... 106
Receiving Data ......................................................... 106
Receiving in 8-Bit or 9-Bit Data Mode ...................... 106
Reception Error Handling ......................................... 106
Transmit Break ......................................................... 106
Transmit Buffer (UxTXB) .......................................... 105
Transmit Interrupt ..................................................... 106
Transmitting Data ..................................................... 105
Transmitting in 8-Bit Data Mode............................... 105
Transmitting in 9-Bit Data Mode............................... 105
UART1 Register Map ............................................... 109
UART2 Register Map ............................................... 109
UART Operation
Idle Mode.................................................................. 108
Sleep Mode .............................................................. 108
Unit ID Locations .............................................................. 141
Universal Asynchronous Receiver Transmitter
(UART) Module......................................................... 103
W
Wake-up from Sleep......................................................... 141
Wake-up from Sleep and Idle ............................................. 64
Watchdog Timer
Timing Requirements ............................................... 187
Watchdog Timer (WDT)............................................ 141, 155
Enabling and Disabling............................................. 155
Operation.................................................................. 155
WWW Address ................................................................. 225
WWW, On-Line Support ....................................................... 9