Datasheet
2010 Microchip Technology Inc. DS70138G-page 221
dsPIC30F3014/4013
Transmission............................................................... 93
I
2
C 7-Bit Slave Mode Operation.......................................... 93
Reception.................................................................... 93
Transmission............................................................... 93
I
2
C Master Mode Operation ................................................95
Baud Rate Generator.................................................. 96
Clock Arbitration.......................................................... 96
Multi-Master Communication,
Bus Collision and Bus Arbitration .......................96
Reception.................................................................... 96
Transmission............................................................... 95
I
2
C Master Mode Support ................................................... 95
I
2
C Module ..........................................................................91
Addresses................................................................... 93
Bus Data Timing Requirements
Master Mode.....................................................201
Slave Mode.......................................................204
General Call Address Support ....................................95
Interrupts.....................................................................95
IPMI Support...............................................................95
Operating Function Description ..................................91
Operation During CPU Sleep and Idle Modes ............ 96
Pin Configuration ........................................................ 91
Programmer’s Model................................................... 91
Register Map...............................................................97
Registers..................................................................... 91
Slope Control .............................................................. 95
Software Controlled Clock Stretching (STREN = 1).... 94
Various Modes ............................................................ 91
I
2
S Mode Operation .......................................................... 129
Data Justification.......................................................129
Frame and Data Word Length Selection................... 129
Idle Current (I
IDLE) ............................................................175
In-Circuit Serial Programming (ICSP) .........................43, 141
Input Capture Module .........................................................81
Interrupts.....................................................................82
Register Map...............................................................83
Input Capture Operation During Sleep and Idle Modes ...... 82
CPU Idle Mode............................................................82
CPU Sleep Mode ........................................................ 82
Input Capture Timing Requirements ................................. 190
Input Change Notification Module....................................... 56
Register Map...............................................................57
Instruction Addressing Modes............................................. 37
File Register Instructions ............................................37
Fundamental Modes Supported..................................37
MAC Instructions......................................................... 38
MCU Instructions ........................................................ 37
Move and Accumulator Instructions............................38
Other Instructions........................................................ 38
Instruction Set
Overview...................................................................162
Summary................................................................... 159
Internal Clock Timing Examples ....................................... 183
Internet Address................................................................ 225
Interrupt Controller
Register Map...............................................................66
Interrupt Priority .................................................................. 60
Traps........................................................................... 62
Interrupt Sequence ............................................................. 63
Interrupt Stack Frame ................................................. 63
Interrupts............................................................................. 59
L
Load Conditions ................................................................181
Low-Voltage Detect (LVD) ................................................155
LVDL Characteristics........................................................ 179
M
Memory Organization ......................................................... 25
Core Register Map ..................................................... 33
Microchip Internet Web Site.............................................. 225
Modes of Operation
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages.................................................. 113
Listen Only................................................................ 113
Loopback.................................................................. 113
Normal Operation ..................................................... 113
Modulo Addressing............................................................. 38
Applicability................................................................. 40
Incrementing Buffer Operation Example .................... 39
Start and End Address ............................................... 39
W Address Register Selection.................................... 39
MPLAB ASM30 Assembler, Linker, Librarian................... 168
MPLAB Integrated Development Environment Software.. 167
MPLAB PM3 Device Programmer .................................... 170
MPLAB REAL ICE In-Circuit Emulator System ................ 169
MPLINK Object Linker/MPLIB Object Librarian................ 168
N
NVM
Register Map .............................................................. 47
O
Operating Current (IDD) .................................................... 174
Operating Frequency vs Voltage
dsPIC30FXXXX-20 (Extended) ................................ 172
Oscillator
Configurations .......................................................... 144
Fail-Safe Clock Monitor .................................... 146
Fast RC (FRC).................................................. 145
Initial Clock Source Selection........................... 144
Low-Power RC (LPRC) .................................... 145
LP Oscillator Control......................................... 145
Phase Locked Loop (PLL)................................ 145
Start-up Timer (OST)........................................ 144
Control Registers...................................................... 147
Operating Modes (Table).......................................... 142
System Overview...................................................... 141
Oscillator Selection........................................................... 141
Oscillator Start-up Timer
Timing Requirements ............................................... 187
Output Compare Interrupts................................................. 88
Output Compare Module .................................................... 85
Register Map dsPIC30F3014 ..................................... 89
Register Map dsPIC30F4013 ..................................... 89
Timing Requirements ............................................... 190
Output Compare Operation During CPU Idle Mode ........... 88
Output Compare Sleep Mode Operation ............................ 88
P
Packaging Information...................................................... 211
Marking..................................................................... 211
Peripheral Module Disable (PMD) Registers.................... 157
Pinout Descriptions............................................................. 13
POR. See Power-on Reset.
Power Saving Modes
Sleep and Idle........................................................... 141
Power-Down Current (I
PD)................................................ 176
Power-Saving Modes........................................................ 155
Idle............................................................................ 156