Datasheet

dsPIC30F3014/4013
DS70138G-page 136  2010 Microchip Technology Inc.
FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 ksps, AUTO-SAMPLE START, 1 TAD
SAMPLING TIME
19.8 A/D Acquisition Requirements
The analog input model of the 12-bit A/D converter is
shown in Figure 19-4. The total sampling time for the
A/D is a function of the internal amplifier settling time
and the holding capacitor charge time.
For the A/D converter to meet its specified accuracy,
the Charge Holding Capacitor (C
HOLD) must be
allowed to fully charge to the voltage level on the
analog input pin. The Source Impedance (R
S), the
Interconnect Impedance (R
IC) and the Internal Sam-
pling Switch (R
SS) Impedance combine to directly
affect the time required to charge the capacitor, CHOLD.
The combined impedance of the analog sources must
therefore be small enough to fully charge the holding
capacitor within the chosen sample time. To minimize
the effects of pin leakage currents on the accuracy of
the A/D converter, the maximum recommended source
impedance, R
S, is 2.5 k. After the analog input chan-
nel is selected (changed), this sampling function must
be completed prior to starting the conversion. The inter-
nal holding capacitor will be in a discharged state prior
to each sample operation.
FIGURE 19-4: 12-BIT A/D CONVERTER ANALOG INPUT MODEL
TCONV
= 14 TAD
TSAMP
= 1 TAD
TSAMP
= 1 TAD
ADCLK
SAMP
DONE
ADCBUF0
ADCBUF1
Instruction Execution BSET ADCON1, ASAM
TCONV
= 14 TAD
CPIN
VA
Rs
ANx
V
T = 0.6V
V
T = 0.6V
I
LEAKAGE
RIC  250
Sampling
Switch
R
SS
CHOLD
= DAC capacitance
V
SS
VDD
= 18 pF
 500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  2.5 k.
RSS  3 k