Datasheet
2010 Microchip Technology Inc. DS70138G-page 135
dsPIC30F3014/4013
Figure 19-2 depicts the recommended circuit for the
conversion rates above 200 ksps. The dsPIC30F3014
is shown as an example.
FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC
The configuration procedures below give the required
setup values for the conversion speeds above
100 ksps.
19.7.1 200 ksps CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 19-2.
• Connect external V
REF+ and VREF- pins following
the recommended circuit shown in Figure 19-2.
• Set SSRC<2.0> = 111 in the ADCON1 register to
enable the auto-convert option.
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register.
• Write the SMPI<3.0> control bits in the ADCON2
register for the desired number of conversions
between interrupts.
• Configure the ADC clock period to be:
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
• Configure the sampling time to be 1 T
AD by
writing: SAMC<4:0> = 00001.
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
AD selection in conjunc-
tion with the guidelines described above allows a con-
version speed of 200 ksps. See Example 19-1 for code
example.
VDD
VDD
VDD
VDD
R2
10
C2
0.1 F
C1
0.01 F
R1
10
C8
1 F
VDD
C7
0.1 F
VDD
C6
0.01 F
AVDD
C5
1 F
AVDD
C4
0.1 F
AVDD
C3
0.01 F
See Note 1
Note 1: Ensure adequate bypass capacitors are provided on each V
DD pin.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
dsPIC30F3014
V
SS
VSS
VDD
VDD
VREF-
VREF+
AV
SS
AVDD
VSS
VDD
VDD
VDD
1
(14 + 1) x 200,000
= 334 ns