Datasheet

dsPIC30F3014/4013
DS70138G-page 124  2010 Microchip Technology Inc.
size and Frame Sync generator control bits. A new I
2
S
data transfer boundary is marked by a high-to-low or a
low-to-high transition edge on the COFS pin.
18.3.6 SLAVE FRAME SYNC OPERATION
When the DCI module is operating as a Frame Sync
slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multichannel mode, a new data frame transfer
begins one CSCK cycle after the COFS pin is sampled
high (see Figure 18-2). The pulse on the COFS pin
resets the Frame Sync generator logic.
In the I
2
S mode, a new data word is transferred one
CSCK cycle after a low-to-high or a high-to-low transi-
tion is sampled on the COFS pin. A rising or falling
edge on the COFS pin resets the Frame Sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame is transferred one CSCK cycle
after the COFS pin is sampled high.
The COFSG and WS bits must be configured to
provide the proper frame length when the module is
operating in the Slave mode. Once a valid Frame Sync
pulse has been sampled by the module on the COFS
pin, an entire data frame transfer takes place. The
module will not respond to further Frame Sync pulses
until the data frame transfer has completed.
FIGURE 18-2: FRAME SYNC TIMING, MULTICHANNEL MODE
FIGURE 18-3: FRAME SYNC TIMING, AC-LINK START-OF-FRAME
FIGURE 18-4: I
2
S INTERFACE FRAME SYNC TIMING
CSCK
CSDI/CSDO
COFS
MSB LSB
Tag
MSb
BIT_CLK
CSDO or CSDI
SYNC
Tag
bit 14
S12
LSb
S12
bit 1
S12
bit 2
Tag
bit 13
MSB LSB MSB
LSB
CSCK
CSDI or CSDO
WS
Note: A 5-bit transfer is shown here for illustration purposes. The I
2
S protocol does not specify word length – this
will be system dependent.