Datasheet

 2010 Microchip Technology Inc. DS70138G-page 101
dsPIC30F3014/4013
15.3 Slave Select Synchronization
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SSx
pin
control enabled (SSEN = 1). When the SSx
pin is low,
transmission and reception are enabled and the SDOx
pin is driven. When SSx pin goes high, the SDOx pin is
no longer driven. Also, the SPI module is resynchro-
nized, and all counters/control circuitry are reset.
Therefore, when the SSx
pin is asserted low again,
transmission/reception begins at the MSb even if SSx
had been deasserted in the middle of a transmit/
receive.
15.4 SPI Operation During CPU Sleep
Mode
During Sleep mode, the SPI module is shut down. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
15.5 SPI Operation During CPU Idle
Mode
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
determines if the SPI module stops or continues on
Idle. If SPISIDL = 0, the module continues to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module stops when the CPU enters Idle mode.