Datasheet

dsPIC30F4011/4012
DS70135G-page 78 © 2010 Microchip Technology Inc.
FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM
FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM
TON
Sync
PR4
T4IF
Equal
Comparator x 16
TMR4
Reset
Event Flag
Q
Q
D
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
T
CY
1
0
TCS
1 x
0 1
TGATE
0 0
Gate
Sync
T4CK
(1)
Note 1: T4CK is not implemented and this line is tied to VSS.
TON
PR5
T5IF
Equal
Comparator x 16
TMR5
Reset
Event Flag
Q
Q
D
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
T
CY
1
0
TCS
1 x
0 1
TGATE
0 0
ADC Event Trigger
Sync
Note: The dsPIC30F4011/4012 devices do not have an external pin input to Timer5. In these devices, the
following modes should not be used:
1. TCS = 1.
2. TCS = 0 and TGATE = 1 (gated time accumulation).