Datasheet

© 2010 Microchip Technology Inc. DS70135G-page 25
dsPIC30F4011/4012
3.0 MEMORY ORGANIZATION
3.1 Program Address Space
The program address space is 4M instruction words. It
is addressable by the 23-bit PC, table instruction
Effective Address (EA) or data space EA, when
program space is mapped into data space as defined
by Table 3-1. Note that the program space address is
incremented by two between successive program
words in order to provide compatibility with data space
addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, read/write instructions,
bit 23 allows access to the Device ID, the User ID and
the Configuration bits; otherwise, bit 23 is always clear.
FIGURE 3-1: PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F4011/4012
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Reset – Target Address
User Memory
Space
000000
00007E
000002
000080
Device Configuration
User Flash
Program Memory
008000
007FFE
Configuration Memory
Space
Data EEPROM
(16K instructions)
(1 Kbyte)
800000
F80000
Registers
F8000E
F80010
DEVID (2)
FEFFFE
FF0000
FFFFFE
Reserved
F7FFFE
Reserved
7FFC00
7FFBFE
(Read ‘0’s)
8005FE
800600
UNITID (32 instr.)
8005BE
8005C0
Reset – GOTO Instruction
000004
Reserved
7FFFFE
Reserved
000100
0000FE
000084
Alternate Vector Table
Reserved
Interrupt Vector Table
Vector Tables