Datasheet

© 2010 Microchip Technology Inc. DS70135G-page 121
dsPIC30F4011/4012
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
This section describes the Universal Asynchronous
Receiver/Transmitter communications module.
18.1 UART Module Overview
The key features of the UART module are:
• Full-Duplex, 8 or 9-bit Data Communication
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Fully Integrated Baud Rate Generator with
16-bit Prescaler
• Baud Rates ranging from 38 bps to 1.875 Mbps at
a 30 MHz Instruction Rate
• 4-Word Deep Transmit Data Buffer
• 4-Word Deep Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for Interrupt Only on Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
FIGURE 18-1: UART TRANSMITTER BLOCK DIAGRAM
Note: This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Write
Write
UTX8
UxTXREG Low Byte
Load TSR
Transmit Control
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Control and Status bits
UxTXIF
Data
‘0’ (Start)
‘1’ (Stop)
Parity
Parity
Generator
Transmit Shift Register (UxTSR)
16 Divider
Control
Signals
16x Baud Clock
from Baud Rate
Generator
Internal Data Bus
UTXBRK
Note: x = 1 or 2. dsPIC30F4012 only has UART1.
UxTX