Datasheet

dsPIC30F4011/4012
DS70135G-page 98 © 2010 Microchip Technology Inc.
FIGURE 15-1: PWM MODULE BLOCK DIAGRAM
PDC3
PDC3 Buffer
PWMCON1
PWMCON2
PTPER
PTMR
Comparator
Comparator
Channel 3 Dead-Time
Generator and
PTCON
SEVTCMP
Comparator
Special Event Trigger
OVDCON
PWM Enable and Mode SFRs
PWM Manual
Control SFR
Channel 2 Dead-Time
Generator and
Channel 1 Dead-Time
Generator and
PWM
Generator 2
PWM
PWM Generator 3
SEVTDIR
PTDIR
DTCON1 Dead-Time Control SFRs
Special Event
Postscaler
PWM1L
PWM1H
PWM2L
PWM2H
Note: Details of PWM Generators 1 and 2 are not shown for clarity.
16-bit Data Bus
PWM3L
PWM3H
FLTACON Fault Pin Control SFRs
PWM Time Base
Output
Driver
Block
FLTA
Override Logic
Override Logic
Override Logic
PTPER Buffer
Generator 1